Storage Controller Data Backup via SRAM Transfer
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Solution Overview
Problem
High-capacity and high-performance storage devices face challenges in reliable data backup due to limited energy from auxiliary power sources, leading to incomplete backups and reduced reliability, especially as data volume increases.
Innovation Solution
A data backup method involving a storage device with a power loss prevention circuit, a storage controller, nonvolatile memory devices, and a buffer memory, which detects power-off events, moves data to static random access memory (SRAM), and programs it to nonvolatile memory devices in a minimum power mode, ensuring efficient energy use and complete backups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If data backup is performed using limited auxiliary power source energy, then power consumption is reduced, but backup completeness and reliability deteriorate
Solution Approach 1:
The system performs preliminary actions by detecting power-off events before complete power loss occurs, initiating data transfer from buffer memory to nonvolatile memory while auxiliary power is still available. This proactive approach ensures critical data is saved before energy is depleted, resolving the contradiction between limited power availability and backup completeness.
Solution Approach 2:
The power loss prevention circuit continuously monitors power source status and provides feedback signals to the storage controller. This feedback mechanism enables the system to adapt its backup operations based on real-time power availability, optimizing the balance between power consumption and backup reliability by adjusting data transfer operations according to remaining auxiliary power levels.
2Speed
If buffer memory power is maintained during power-off event, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts buffer memory power state based on operational requirements. During normal operation, buffer memory remains powered for high-speed data transfer. Upon detecting a power-off event, the system transitions buffer memory to a low-power state after completing critical data transfers, optimizing the dynamic balance between transfer speed and power consumption during the transition period.
Solution Approach 2:
The system implements periodic power management by cycling buffer memory power states according to backup progress. Power is maintained during active data transfer phases and reduced during completion phases, creating a periodic pattern that balances speed requirements with energy conservation throughout the backup process.
3Reliability
If host interface is kept active during power-off event, then data access reliability is improved, but power consumption increases
Solution Approach 1:
The system segments the host interface functionality into critical and non-critical components. Critical data transfer functions remain active to ensure backup reliability, while non-critical host communication functions are deactivated to reduce power consumption. This segmentation allows the system to maintain essential data access reliability while minimizing unnecessary power usage during power-off events.
Data Source
AI summary
A data backup method of a storage device which includes a storage controller, a buffer memory, and a plurality of nonvolatile memory devices, the method including: detecting a power-off event of an external power provided to the storage device; deactivating a host interface of the storage controller in response to the detection of the power-off event; moving data stored in the buffer memory to a static random access memory (SRAM) in the storage controller; blocking or deactivating a power of the buffer memory; setting an interleaving mode of the plurality of nonvolatile memory devices to a minimum power mode; and programming the data moved to the SRAM to at least one of the plurality of nonvolatile memory devices.