Storage Controller Scheduling for Uneven Word Line Program Times

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Solution Overview

Problem

The increasing size of memory blocks in non-volatile memory devices leads to varying program times between word lines, affecting data reliability and performance, and the erase operations cause peak power consumption.

Innovation Solution

A storage device and method that includes a storage controller to manage program and erase operations across multiple non-volatile memory devices, utilizing a word line table to allocate memory blocks based on consistent program times and distribute erase operations, ensuring interleaving operations and reducing power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of memory block increases to increase capacity, then integration density is improved, but difference in program time between word lines increases

Engineering Contradiction:
ImprovecapacityVSAvoidprogram time consistency
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The memory block is divided into multiple sub-blocks, each containing a specific range of word lines. The controller manages programming operations on a per-sub-block basis, allowing fine-grained control over program times. This segmentation enables the system to handle the large memory block capacity while maintaining program time consistency through selective sub-block programming.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The controller dynamically adjusts programming parameters such as voltage levels and pulse widths based on the specific word line being programmed. By monitoring and adapting these parameters in real-time, the system compensates for variations in program time across different word lines within the same memory block, thereby maintaining consistent programming performance despite the increased block size.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If erase operations are performed on memory blocks, then data reliability is improved, but peak power consumption increases

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The erase operation is segmented to target only specific sub-blocks that require erasure rather than entire memory blocks. The controller identifies and erases only the necessary sub-blocks containing invalid or stale data, significantly reducing the power consumption associated with erase operations while maintaining data reliability through selective rejuvenation of memory regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary identification of sub-blocks requiring erasure before executing the erase operation. By pre-processing to determine which sub-blocks need erasure based on wear leveling metrics and data validity, the system avoids unnecessary erase operations on already healthy sub-blocks, thereby reducing peak power consumption while ensuring data reliability is maintained where needed.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250378024A1Storage device and operating method thereof for reducing difference in program time between word lines
Publication Date: 2025.12.11 SAMSUNG ELECTRONICS CO LTD
  • US20250378024A1 patent drawing
  • US20250378024A1 patent drawing
  • US20250378024A1 patent drawing

AI summary

A storage device includes a plurality of non-volatile memory devices and a storage controller configured to generate program commands and first addresses corresponding to a plurality of word lines included in a first super block based on a sequential write request from a host, determine whether to allocate at least one sub-memory block included in a second super block based on data of a word line table which indicate word lines having a relatively small program time and the first addresses, and generate at least one erase command and at least one second address corresponding to the allocated at least one sub-memory block for performing an erase operation.