Directly-Addressable Storage Data Durability Signaling
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Solution Overview
Problem
Storage systems face challenges in ensuring data durability and efficiency, particularly in moving data from volatile to non-volatile memory in directly-addressable storage devices like SSDs, which can result in data loss during power outages and increased processor overhead.
Innovation Solution
Implementing data durability signaling through interrupts and PCIe multicasting logic that determines the address of write commands to copy data efficiently between processor memory and directly-addressable storage devices, ensuring data is committed to non-volatile memory with reduced processor involvement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to volatile memory in directly-addressable storage devices for fast access, then I/O performance is improved, but data durability deteriorates due to potential data loss during power outages
Solution Approach 1:
The patent introduces an intermediary interrupt mechanism that mediates between the volatile memory write operations and the non-volatile memory commit operations. When data is written to volatile memory, an interrupt is generated that triggers a background process to commit the data to non-volatile memory, thus protecting data durability while maintaining fast I/O performance through volatile memory caching
Solution Approach 2:
The system performs preliminary writing of data to volatile memory to achieve fast I/O performance, then subsequently commits the data to non-volatile memory through interrupt-triggered background operations. This preliminary action approach allows the system to accept writes quickly while ensuring durability through follow-up persistence operations
2Reliability
If the processor directly manages data copying between processor memory and storage device memory, then data durability is ensured, but processor overhead increases
Solution Approach 1:
The directly-addressable storage device is empowered to self-manage the commit operation from volatile memory to non-volatile memory. Upon receiving an interrupt signal, the storage device autonomously performs the data persistence operation without requiring continuous processor intervention, thus reducing processor overhead while ensuring data durability
Solution Approach 2:
The interrupt mechanism serves as a feedback signal that triggers the commit operation. When data is written to volatile memory, an interrupt is generated that provides feedback to the storage device, initiating the background commit process to non-volatile memory. This feedback-driven approach ensures durability while minimizing processor involvement
3Reliability
If multiple write commands are processed sequentially by the processor, then data durability is maintained, but latency increases
Solution Approach 1:
Multiple write commands are preliminarily processed and executed in the background through interrupt-driven operations rather than waiting for sequential processor confirmation. The processor can issue multiple write commands quickly to volatile memory, and the commits to non-volatile memory are performed subsequently in the background, reducing latency while maintaining durability
Solution Approach 2:
The system maintains continuous useful action by allowing the processor to issue write commands without waiting for commit confirmation. The background commit process continues to execute persistence operations asynchronously, ensuring that the processor can maintain high throughput while data durability is ensured through continuous background commitment operations
Data Source
AI summary
A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.