Storage Data Interleaving for Burst Error QoS Control
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Solution Overview
Problem
Storage systems face challenges in handling burst errors and latency, particularly in three-dimensional flash memory, which can impact the quality of service for media applications, as existing error correction algorithms may not suffice to handle these issues without increasing write amplification through redundancy.
Innovation Solution
The implementation of data interleaving in storage systems, where the controller determines a skip length based on various factors such as frame size, group of pictures, archive status, or history of failures, to spread out data storage, thereby minimizing the impact of burst errors and latency, and updating the logical-to-physical address table to reflect the interleaved data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored redundantly using RAID to protect against burst errors and latency, then reliability is improved, but write amplification increases
Solution Approach 1:
The patent segments consecutive data units and distributes them across different physical locations in memory using an interleaving pattern. Instead of storing redundant copies of entire data blocks (RAID approach), the system divides data into units and spaces them out by a calculated skip length, so that burst errors affecting one location do not impact consecutive data units. This segmentation approach provides error protection without the write amplification overhead of traditional redundancy schemes.
Solution Approach 2:
The patent introduces a new dimension of protection by interleaving data across multiple memory planes or channels. By distributing data units across different physical dimensions (planes, channels, or memory blocks) rather than simply duplicating data, the system achieves reliability improvements without proportional increases in write amplification. The skip length calculation determines the spacing pattern across these dimensions.
2Reliability
If error correction algorithms are strengthened to handle burst latency, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by interleaving data during the write operation before data is stored in memory. This proactive distribution of data units across different locations prevents burst errors from affecting consecutive data, eliminating the need for complex error correction algorithms during read operations. The skip length is calculated in advance based on expected burst error characteristics, and data is distributed accordingly before storage.
Solution Approach 2:
The patent converts the harmful effect of burst errors into a benefit by using the interleaving pattern to distribute data such that burst errors naturally affect non-consecutive data units. Instead of trying to correct burst errors through complex algorithms, the system transforms the burst error characteristic into a manageable issue where only isolated data units are affected, which can be handled by simpler error correction mechanisms.
3Productivity
If data is stored sequentially without interleaving, then productivity is improved, but reliability deteriorates due to burst errors and latency
Solution Approach 1:
The patent introduces dynamics by making the skip length adjustable rather than fixed. The skip length can be modified based on the type of data being written, memory configuration, and observed error patterns. For example, different skip lengths can be used for video data versus archival data, or the skip length can be adapted based on measured burst error characteristics. This dynamic approach maintains high write throughput while adapting reliability to specific operational conditions.
Solution Approach 2:
The patent changes the parameter of data spacing by implementing variable skip lengths in the interleaving pattern. Instead of always using fixed spacing, the system can adjust the skip length parameter based on data characteristics, memory plane configuration, and performance requirements. This parameter change allows optimization of both write speed and error resistance for different workloads and memory configurations.
Data Source
AI summary
A storage system and method for interleaving data for enhanced quality of service are provided. In one embodiment, a storage system is presented comprising a memory and a controller. The controller is configured to determine a skip length for interleaving data received from a host; interleave the data according to the determined skip length; store the interleaved data in the memory; and update a logical-to-physical address table to reflect the interleaved data. Other embodiments are provided.