Storage Device Detector Configuration Switching

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Solution Overview

Problem

Current data storage devices face challenges in efficiently recovering data due to signal impairments such as weak writes, adjacent track interference, thermal decay, and track mis-registration, which alter read-back signal characteristics, leading to reduced areal density capabilities and increased data recovery time.

Innovation Solution

The implementation of a storage device that switches between different detector configuration sets during decoding iterations, allowing for real-time adaptation of SOVA parameters to match changing signal conditions, thereby optimizing data recovery without the need for excessive margin in areal density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single detector configuration is used for all decoding iterations, then device complexity is reduced, but data recovery time increases under varying signal conditions

Engineering Contradiction:
Improvedetector configurationVSAvoiddata recovery time
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the detector configuration changeable during decoding iterations. Multiple configuration sets are stored in memory, and the detector dynamically switches between them based on decoding progress and signal conditions, allowing the system to adapt to varying signal characteristics without permanent hardware changes

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes detector parameters by loading different configuration sets that contain various SOVA parameters. These parameter sets are adjusted based on iteration number and signal quality metrics, enabling the detector to optimize its performance for different decoding stages and signal conditions

Inventive Principle:
Principle #35Parameter changes

2Productivity

If detector configuration is dynamically adjusted during decoding iterations, then data recovery speed improves, but device complexity increases

Engineering Contradiction:
Improvedata recovery speedVSAvoiddetector configuration management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent prepares multiple configuration sets in advance and stores them in memory before decoding begins. This preliminary preparation allows the detector to quickly switch between pre-optimized configurations during decoding without real-time computation overhead, maintaining high data recovery speed

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from decoding performance and signal quality metrics to determine which configuration set to load next. The processor monitors decoding progress and adjusts the detector configuration accordingly, creating a closed-loop system that optimizes recovery speed based on actual performance

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If margin is reduced in areal density to increase capacity, then storage capacity improves, but signal impairments increase leading to slower data recovery

Engineering Contradiction:
Improvestorage capacityVSAvoiddata recovery time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent compensates for signal impairments from reduced areal density margins by dynamically changing detector parameters. Multiple configuration sets with different SOVA parameters allow the system to counteract the increased noise and interference from higher density storage, maintaining fast data recovery speeds

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11495260B1Storage device that switches detector configuration sets between decoding iterations
Publication Date: 2022.11.08 SEAGATE TECH LLC
  • US11495260B1 patent drawing
  • US11495260B1 patent drawing
  • US11495260B1 patent drawing

AI summary

A plurality of configuration sets are used with a detector coupled to a decoder. A processor is coupled to the memory registers and the detector and operable to load a first one of the configuration sets into the detector. The detector to attempts detection of the bits in the digital stream for a first iteration between the detector and the decoder using the first configuration set. After the first iteration, a second one of the configuration sets is loaded into the detector. The second configuration set is different than the first configuration set. The detector to attempts detection of the bits in the digital stream for a second iteration between the detector and the decoder using the second configuration set.