Storage Device Address Translation Lookup Table
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage devices incur significant timing overhead due to the need for cumulative calculations to translate logical addresses to physical addresses during each register read operation, limiting data rates and increasing latency.
Innovation Solution
The storage device performs these calculations during a power-on-read (POR) operation, identifying and storing pointers for bad physical addresses, allowing subsequent register read operations to directly use pre-calculated pointers, reducing the need for on-the-fly calculations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If address translation calculations are performed during each register read operation, then data can be retrieved from physical memory locations, but timing overhead accumulates and reduces overall data rates
Solution Approach 1:
The patent pre-calculates and stores the mapping between logical addresses and physical memory locations in a translation lookup table (TLT) during system initialization. This eliminates the need to perform address translation calculations during each register read operation, as the mappings are readily available in the TLT, thereby resolving the contradiction between ensuring accurate data retrieval and maintaining high data rates
Solution Approach 2:
The patent creates a copy of the address translation mappings in the TLT, which is a simplified version of the full address translation process. Instead of performing complete address translation calculations for each read operation, the system uses the pre-computed TLT copy to quickly determine physical locations, thus maintaining reliability while improving productivity
2Ease of operation
If cumulative timing overhead is incurred for each register read operation, then address translation can be completed, but overall latency increases and performance deteriorates
Solution Approach 1:
The TLT is populated with all necessary address translation mappings during system initialization before any register read operations occur. This preliminary action ensures that complete address translation capability is available while eliminating the time-consuming cumulative overhead that would otherwise occur during each subsequent read operation
Solution Approach 2:
The patent replaces the mechanical calculation process of address translation with a lookup operation in the TLT. Instead of performing computational operations during each read, the system substitutes this with a simple memory access to retrieve pre-computed mappings, significantly reducing read latency while maintaining translation completeness
Data Source
AI summary
Aspects of a storage device are provided that reduce calculations for identifying physical locations of data during a read operation. In one aspect, a memory device includes one or more memory arrays. Each array includes multiple chunks of memory. The device includes a first set of registers for storing prefixed starting addresses for each array. The device further includes control logic that may identify bad physical address in each array. For each successive chunk in each array and based on the prefixed starting address and the bad physical address locations, the device may determine a pointer to a starting physical address for the chunk. The pointer may be stored in a second set of registers for use in register read operations.