Storage Device Buffer Memory Access Interference Management
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Solution Overview
Problem
Existing storage devices face challenges in efficiently managing multiple access interference when multiple master IP blocks access a buffer memory, leading to suboptimal performance in flash memory-based mass storage media.
Innovation Solution
A storage device is designed with a buffer memory, multiple DMA circuits, an address translation circuit, and a buffer controller to provide direct memory access and reduce interference by translating virtual addresses into physical addresses and distributing accesses among multiple memory banks, allowing parallel processing and efficient use of the buffer memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple master IP blocks access a buffer memory simultaneously, then data transmission capability is improved, but access interference increases
Solution Approach 1:
The buffer memory is divided into multiple memory banks (first memory bank, second memory bank, etc.) that can operate independently. Each master IP block is assigned to access specific memory banks, allowing simultaneous operations without interference. The address translation circuit translates virtual addresses to physical addresses of specific memory banks, enabling parallel data transmission while managing access rights.
2Measurement precision
If virtual address translation is performed for all addresses, then address management precision is improved, but translation time increases
Solution Approach 1:
The address translation circuit selectively translates virtual addresses to physical addresses based on the reference range. When a virtual address falls within the reference range, translation is performed to assign specific memory banks. When the address is outside the reference range, translation is skipped and the virtual address is used directly. This localized translation approach maintains address management precision for critical areas while reducing unnecessary translation time.
Data Source
AI summary
A storage device includes a buffer memory, a first direct memory access (DMA) circuit configured to provide data from a host to the buffer memory or data stored in the buffer memory to the host and output a first virtual address, a second DMA circuit configured to provide data read from a non-volatile memory to the buffer memory or the data stored in the buffer memory to the non-volatile memory and output a second virtual address, an address translation circuit configured to translate the first or second virtual address into a physical address when the first or second virtual address is included in a reference range and skip the translation operation when the first or second virtual address is excluded in the reference range. A buffer controller is configured to access the buffer memory based on the physical address of the first or second virtual address that is excluded.