Storage Device Supporting Byte and Block Accessible Interfaces
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Solution Overview
Problem
The complexity and cost of designing systems that utilize both dynamic random access memory (DRAM) for fast byte-access and NAND flash memory for block-access, due to their different functionalities and requirements, lead to inefficiencies in data transfer and increased design complexity.
Innovation Solution
A storage device and electronic system that supports both byte and block accessible interfaces through a first memory device accessed by units of bytes and a second memory device accessed by units of blocks, with an internal transfer controller managing data transfer between them using modified internal transfer commands based on block access commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If both DRAM and NAND flash memory are used in separate systems, then byte-access speed and block-access capacity are improved, but design complexity and manufacturing cost increase
Solution Approach 1:
The patent combines DRAM and NAND flash memory into a single storage device, allowing the host to access both byte-addressable (DRAM) and block-addressable (NAND flash) memory through unified interfaces. This merging eliminates the need for separate systems while maintaining both fast byte-access and high-capacity block-access capabilities, thereby reducing design complexity and manufacturing cost.
Solution Approach 2:
The storage device provides multiple access interfaces (byte-accessible interface for DRAM and block-accessible interface for NAND flash) within a single device, enabling it to perform both byte-level and block-level operations. This multi-functionality allows the system to handle diverse workloads without requiring separate specialized devices.
2Productivity
If both DRAM and NAND flash memory are used in separate systems, then byte-access speed and block-access capacity are improved, but manufacturing cost increases
Solution Approach 1:
By integrating DRAM and NAND flash memory chips into a single storage device package, the patent reduces the total number of components and interconnections required in the system. This consolidation simplifies the manufacturing process and reduces assembly costs while maintaining both high-capacity block-access and fast byte-access capabilities.
3Adaptability or versatility
If separate memory systems are used, then specialized functionality is achieved, but data transfer efficiency decreases
Solution Approach 1:
The patent introduces an internal transfer controller that acts as an intermediary between the DRAM and NAND flash memory components. This controller enables direct internal data transfer between the two memory types without requiring data to be routed through external host interfaces, thereby reducing transfer time and energy consumption while maintaining specialized functionality for both byte-access and block-access operations.
Data Source
AI summary
An electronic system includes a host device and a storage device. The storage device includes a first memory device that is accessed by the host device by units of a byte through a byte accessible interface and a second memory device that is accessed by the host device by units of a block through a block accessible interface. The storage device performs an internal data transfer between the first memory device and the second memory device based on an internal transfer command that is provided through the block accessible interface from the host device. The electronic system may efficiently support the access by units of a byte and the access by units of a block between the host device and the storage device by performing internal data transfer in the storage device using the internal transfer command that is modified from the existing block access command.