Storage Device Check Read Voltage Selection for Latency Reduction

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Solution Overview

Problem

The high degree of integration in semiconductor storage devices leads to reduced reliability and increased latency due to the need for additional time for reliability checks, which can decrease throughput.

Innovation Solution

A storage device with a nonvolatile memory device and memory controller that performs sequential check read operations on neighbor pages using sets of read voltages, selecting those that succeed in error correction to reduce the time required for check read operations while maintaining reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If reliability check methods are introduced to prevent data damage, then reliability is improved, but latency increases and throughput decreases

Engineering Contradiction:
Improvestorage device reliabilityVSAvoidcheck operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs check read operations on neighbor pages in advance before actual data read operations. By proactively checking adjacent pages that are likely to be accessed soon, the system prepares reliability verification results ahead of time, so when actual read operations occur, the reliability check can be completed or nearly completed, reducing the perceived latency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent dynamically adjusts the check operation strategy by identifying and prioritizing neighbor pages based on access patterns. Instead of uniformly checking all pages, the system adaptively selects which neighbor pages to check first, optimizing the balance between reliability verification and time consumption based on actual usage scenarios.

Inventive Principle:
Principle #15Dynamics

2Reliability

If check read operations are performed on all neighbor pages, then reliability is improved, but throughput decreases due to increased operation time

Engineering Contradiction:
Improvedata reliabilityVSAvoidstorage device throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different check operation intensities to different pages. Neighbor pages that are more likely to be accessed (identified through access pattern analysis) receive priority checking with more thorough verification, while less frequently accessed pages receive reduced checking. This localized quality approach ensures reliability for critical pages without uniformly increasing the time for all operations, thus preserving throughput.

Inventive Principle:
Principle #3Local quality

3Reliability

If the number of check read operations is increased to cover more neighbor pages, then reliability is improved, but latency increases

Engineering Contradiction:
Improveneighbor page reliabilityVSAvoidcheck operation latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent changes the parameter of check operation scope by selectively adjusting which neighbor pages are checked and in what order. Instead of increasing the total number of checks uniformly, the system modifies the check scope parameter dynamically based on access patterns, focusing verification efforts on the most relevant neighbor pages. This reduces unnecessary checks on pages unlikely to be accessed, lowering latency while maintaining reliability for pages that matter.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11961559B2Storage device and operating method of storage device
Publication Date: 2024.04.16 SAMSUNG ELECTRONICS CO LTD
  • US11961559B2 patent drawing
  • US11961559B2 patent drawing
  • US11961559B2 patent drawing

AI summary

A storage device includes a nonvolatile memory device and a memory controller allowing the nonvolatile memory device to perform a read operation on memory cells belonging to a selected page in a selected memory block. After the read operation, the memory controller allows the nonvolatile memory device to perform a first check read operation on memory cells of a first neighbor page while sequentially selecting sets of read voltages. After the first check read operation, the memory controller allows the nonvolatile memory device to perform a second check read operation on memory cells of a second neighbor page while sequentially selecting the sets of read voltages. In the second check read operation, the memory controller first selects a set of read voltages, which are used in the first check read operation in which error correction succeeds.