Storage Device Data Training Using Delayed Signals

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Solution Overview

Problem

The increasing operating speed of memory devices makes it challenging to ensure the reliability of data transmission, requiring longer training times to align transmission timings of data signals effectively.

Innovation Solution

A storage device configuration that includes a first chip transmitting data signals with different delay times and a second chip sampling these signals using a data strobe signal, allowing for rapid detection of the data strobe signal (DQS) delay time, thereby reducing the overall data training time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If operating speed of memory devices is increased, then productivity is improved, but reliability of data transmission deteriorates

Engineering Contradiction:
Improveoperating speedVSAvoiddata transmission reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by performing data training before normal data transmission operations. The training process pre-adjusts the timing of data signals and strobe signals to account for delays in the data path, ensuring that when actual data transmission occurs at high speeds, the signals are already synchronized and reliable. This includes transmitting training data signals with intentional delays and adjusting strobe signal timing based on the observed sampling results.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If training time is increased to align data signal timings, then reliability is improved, but loss of time increases

Engineering Contradiction:
Improvedata transmission reliabilityVSAvoidtraining time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the data signals into multiple groups, where each group is transmitted with a different intentional delay time. By dividing the training process into discrete segments with controlled delays, the system can efficiently determine the optimal strobe signal timing without requiring exhaustive testing of all possible delay values. This segmentation approach reduces the overall training time while maintaining reliable data transmission.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by transmitting only a limited set of training data signals with specific predetermined delays, rather than testing all possible delay values. This selective approach provides sufficient information to determine the optimal timing alignment without requiring complete exhaustive testing, thereby reducing training time while achieving reliable data transmission.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If multiple data signals with different delay times are transmitted for training, then measurement precision of DQS delay time is improved, but device complexity increases

Engineering Contradiction:
ImproveDQS delay time detection precisionVSAvoidtraining signal configuration complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the delay time parameter of data signals in a systematic and controlled manner during training. By varying only the delay time parameter while keeping other signal characteristics constant, the system can precisely measure the optimal DQS delay time without introducing unnecessary complexity. This parameter-based approach allows for efficient training signal configuration and evaluation.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20240212729A1Storage device and data training method thereof
Publication Date: 2024.06.27 SAMSUNG ELECTRONICS CO LTD
  • US20240212729A1 patent drawing
  • US20240212729A1 patent drawing
  • US20240212729A1 patent drawing

AI summary

A storage device includes a first chip and a second chip configured to exchange data with the first chip. The first chip may transmit a data strobe signal and a plurality of data signals, applied with different delay times, to the second chip. The second chip may sample the plurality of data signals, applied with the different delay times, using the data strobe signal received from the first chip during data training.