Storage Device Data Transfer Optimization via Dual Memory Segmentation

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Solution Overview

Problem

Flash memory devices face limitations in increasing speed without enlarging access units, requiring erase blocks that are tens of times larger than access units, leading to degraded write efficiency and low transfer performance, especially when replacing hard disks in applications like mobile devices where power consumption and portability are concerns.

Innovation Solution

A storage device with a control circuit that dynamically moves data between a first memory unit requiring erasure for rewriting and a second memory unit with faster rewriting speeds, using an address conversion table to manage page data and invalidate original page regions, allowing for flexible data assignment based on access characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If flash memory uses traditional erasure-based rewriting, then data can be stored non-volatily, but write speed is slow and transfer performance is limited

Engineering Contradiction:
Improvewrite speedVSAvoidmemory structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The memory device is segmented into two distinct memory units: a first memory unit (flash memory) for non-volatile storage and a second memory unit (high-speed memory) for fast data operations. This segmentation allows each memory type to operate in its optimal performance range, with the high-speed memory handling frequent write operations without requiring erasure cycles.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The second memory unit acts as an intermediary between the external interface and the first memory unit. It buffers data during write operations, enabling high-speed data transfer while the slower flash memory performs erasure and programming operations in the background, thus decoupling the speed requirements of different operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If flash memory enlarges access units to increase speed, then transfer performance improves, but write efficiency degrades due to larger erase blocks

Engineering Contradiction:
Improvetransfer speedVSAvoidwrite energy efficiency
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

Different memory units are assigned different local qualities: the first memory unit provides non-volatile storage with standard access patterns, while the second memory unit provides high-speed access with smaller effective access units. This allows the system to achieve high transfer speeds for frequently accessed data without forcing the entire flash memory to use inefficiently large erase blocks.

Inventive Principle:
Principle #3Local quality

3Reliability

If flash memory requires erasure before rewriting, then data integrity is maintained, but redundant write operations increase

Engineering Contradiction:
Improvedata integrityVSAvoidwrite efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs preliminary actions by pre-erasing or pre-loading data into the second memory unit before actual write operations are needed. This allows the flash memory to be ready for immediate high-speed writing without requiring erasure cycles at the moment of write, thus maintaining data integrity while improving write efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Data is copied between the two memory units as needed. The second memory unit can hold copies of frequently accessed or recently written data, reducing the need for repeated erasure and rewrite cycles in the flash memory, thereby improving overall write efficiency while maintaining data integrity through controlled copy operations.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS8554982B2Storage device and information processing system
Publication Date: 2013.10.08 SONY GROUP CORP
  • US8554982B2 patent drawing
  • US8554982B2 patent drawing
  • US8554982B2 patent drawing

AI summary

A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.