Storage Device Dual Error Correction Circuit Mapping Memory
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Solution Overview
Problem
Existing semiconductor devices struggle to maintain a low write error rate (WER) after the manufacturing stage, which affects the reliability of the storage devices.
Innovation Solution
The proposed solution involves a storage device with a controller that includes a first and second error correction circuit, a mapping memory, and a control block. The second error correction circuit has a greater maximum number of correctable error bits than the first, and the mapping memory stores parity bits generated by the second error correction circuit along with the address of the memory device. This configuration allows for improved WER management post-manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single error correction circuit is used, then device complexity is reduced, but reliability deteriorates due to insufficient error correction capability after manufacturing
Solution Approach 1:
The error correction circuit is divided into two separate circuits: a first error correction circuit for basic error correction and a second error correction circuit for enhanced error correction. Each circuit handles specific error correction tasks, allowing the system to achieve high reliability without requiring a single overly complex circuit. The segmentation enables independent optimization of each circuit's functionality.
Solution Approach 2:
The system implements partial error correction by using the first error correction circuit for routine operations and reserving the second error correction circuit for situations requiring enhanced protection. This partial action approach allows the system to maintain high reliability when needed while avoiding the constant overhead of maximum error correction capability.
2Reliability
If parity bits are stored only in the memory device, then device complexity is reduced, but reliability deteriorates due to insufficient error correction coverage
Solution Approach 1:
The storage structure is segmented into two parts: the memory device stores original data and some parity bits, while the mapping memory stores addresses and remaining parity bits. This segmentation allows the system to distribute error correction information across multiple storage locations, enhancing error correction coverage without requiring all parity bits to be stored in a single location.
Solution Approach 2:
The mapping memory acts as an intermediary between the memory device and the error correction circuits. It stores addresses and parity bits that bridge the gap between the primary storage location and the error correction functionality, enabling the system to access and utilize error correction information efficiently without direct complexity in the memory device itself.
3Reliability
If the second error correction circuit is used for all data, then reliability is improved, but device complexity increases due to redundant error correction capability
Solution Approach 1:
The error correction circuit operation is made dynamic by selectively activating the first or second error correction circuit based on the specific data being processed. The control block determines which circuit to use in real-time, allowing the system to adapt its error correction capability to the current operational requirements rather than always using the maximum capability.
Solution Approach 2:
The system applies partial error correction by using the first error correction circuit for standard operations and reserving the second error correction circuit for enhanced protection when needed. This partial action approach allows the system to maintain high reliability when required while avoiding the constant computational overhead of maximum error correction capability.
Data Source
AI summary
Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.