Storage Device Dual Map Cache Architecture for Address Translation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current storage devices face inefficiencies in obtaining physical addresses, leading to slower operation speeds due to the lack of effective caching mechanisms for mapping information between logical and physical addresses.
Innovation Solution
A storage device architecture that incorporates a nonvolatile memory device for storing map data, a volatile memory device with two cache areas (one for map entries and another for map indexes) to quickly retrieve physical addresses, and a memory controller to manage these caches and perform operations based on the obtained addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If map data is stored only in nonvolatile memory device, then data persistence is maintained, but physical address obtainment speed deteriorates
Solution Approach 1:
The patent divides the caching system into two distinct segments: a first cache area for storing frequently accessed map data and a second cache area for storing less frequently accessed map data. This segmentation allows the system to optimize access speed for hot data while maintaining a larger caching capacity in the second area, thereby improving physical address obtainment speed without compromising data persistence as the ultimate storage remains in nonvolatile memory.
Solution Approach 2:
The patent introduces a volatile memory device as an intermediary between the host and the nonvolatile memory device. This intermediary contains cache areas that temporarily store map data, acting as a buffer that speeds up address translation operations while the nonvolatile memory device maintains the authoritative persistent storage. The intermediary resolves the speed-persistence contradiction by providing fast access paths for operational data while preserving data durability.
2Speed
If volatile memory is used for caching map data, then physical address obtainment speed is improved, but power consumption increases
Solution Approach 1:
The patent implements a periodic refresh mechanism for the cache areas in volatile memory. Instead of continuously powering all cache regions, the system periodically refreshes only those cache areas that contain currently valid and frequently accessed map data. This periodic action maintains the speed benefits of volatile memory caching while reducing overall power consumption by allowing parts of the volatile memory to enter low-power states when not actively being accessed.
Solution Approach 2:
The patent applies different quality characteristics to different parts of the caching system. The first cache area uses high-speed volatile memory for frequently accessed map data, while the second cache area may use slower memory or different retention characteristics. This local differentiation optimizes the balance between speed and power consumption by providing high-performance caching only where it is most needed, rather than uniformly across the entire system.
3Device complexity
If only one cache area is used for map data, then device complexity is reduced, but address translation efficiency deteriorates
Solution Approach 1:
The patent segments the cache structure into a first cache area and a second cache area with different functions and optimization characteristics. The first cache area is optimized for speed and stores hot map data, while the second cache area provides additional capacity for less frequently accessed data. This segmentation improves address translation efficiency by allowing the system to serve different types of access patterns from appropriately optimized cache regions, without creating excessive complexity through a single monolithic cache structure.
Solution Approach 2:
The patent implements dynamic cache management where the system can adaptively allocate and manage the two cache areas based on access patterns and system state. The controller can dynamically determine which cache area to use for specific address translation operations, and can dynamically manage the contents and size of each cache area. This dynamic approach improves productivity by optimizing cache utilization in real-time while maintaining manageable device complexity through systematic control mechanisms.
Data Source
AI summary
The present technology relates to an electronic device. According to the present technology, a storage device having an improved physical address obtainment speed may include a nonvolatile memory device configured to store map data including a plurality of map segments including mapping information and, a volatile memory device including a first map cache area temporarily storing the map data configured by map entries each corresponding to one logical address, and a second map cache area temporarily storing the map data configured by map indexes each corresponding to a plurality of logical addresses.