Storage Device Global Wear-Leveling Through Targeted Core Data Swaps
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Solution Overview
Problem
The lifetime and performance of storage devices are adversely affected by uneven wear and tear of memory components, leading to reduced performance and potential degradation.
Innovation Solution
Implementing a global wear-leveling method that involves counting write counts of multiple cores within logical areas, identifying cores for data swap based on degradation counts, and performing targeted data swaps to balance wear across memory components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data swap is performed between cores with different degradation counts, then wear distribution is improved, but internal I/O operations increase
Solution Approach 1:
The patent applies local quality by performing data swap operations selectively only in logical areas where the write count difference between cores exceeds a predetermined threshold. This means that wear-leveling is applied locally to specific degraded areas rather than globally across the entire memory, thereby reducing unnecessary internal I/O operations while still improving wear distribution where needed.
Solution Approach 2:
The patent implements partial action by performing data swap only for logical block address groups in logical areas that meet the wear imbalance criterion. Instead of swapping all data across all cores, the system performs partial swaps only where degradation differences are significant, thus balancing wear distribution while minimizing the overhead of internal I/O operations.
2Duration of action of stationary object
If global wear-leveling is performed across all logical areas, then lifetime is extended, but device complexity increases
Solution Approach 1:
The patent segments the memory into multiple logical areas, each containing multiple logical block address groups. This segmentation allows the wear-leveling process to be divided into manageable units, where only specific segments (logical areas with significant wear imbalance) require data swap operations. This reduces the overall complexity compared to a global wear-leveling approach that would treat the entire memory uniformly.
Solution Approach 2:
The patent applies local quality by implementing wear-leveling selectively in specific logical areas rather than uniformly across all areas. The controller identifies logical areas where the write count difference between cores exceeds a threshold and performs data swap only in those areas, thereby extending memory lifetime while avoiding the complexity of global wear-leveling operations.
3Reliability
If data swap is performed frequently, then wear distribution is improved, but performance degradation increases
Solution Approach 1:
The patent implements periodic action by performing data swap operations based on monitored write count differences rather than continuously or at fixed time intervals. The controller periodically checks the write count difference between cores and performs data swap only when the difference exceeds a predetermined threshold, thereby maintaining good wear distribution while minimizing performance degradation from frequent operations.
Solution Approach 2:
The patent uses feedback by continuously monitoring the write count difference between cores and using this information to decide when data swap operations are necessary. The controller adjusts its wear-leveling actions based on the actual wear state of different cores, performing data swap only when the feedback indicates significant wear imbalance, thus optimizing both wear distribution and device performance.
Data Source
AI summary
A storage device, a controller, and a method for performing global wear-leveling may count write counts of a plurality of respective cores in each of a plurality of logical areas each including logical block address groups of the plurality of cores, determine, on the basis of degradation counts of the plurality of cores, a first core and a second core for which data swap is to be performed, determine a target logical area among the plurality of logical areas on the basis of a write count of the first core and a write count of the second core, and perform data swap between a first logical block address group of the first core included in the target logical area and a second logical block address group of the second core included in the target logical area.