Storage Device Interrupt Control via Buffer Thresholds
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Solution Overview
Problem
The existing solid storage devices face challenges in efficiently managing cache memory, leading to increased complexity for the controller and potential performance bottlenecks, especially when the cache is fully occupied, and the power provided by capacitors limits the size of the buffer memory due to faster semiconductor technology advancements.
Innovation Solution
A method for controlling interrupts in storage devices that includes a flash memory and a buffer memory, where data is written to the buffer memory and then to the flash memory, with messages indicating write operation completion only when the buffer memory data is below a predetermined threshold, allowing flexible host control and optimizing standby power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to improve reading and writing speed, then storage performance is improved, but controller complexity increases and host experiences performance bumps when cache is fully occupied
Solution Approach 1:
The patent extracts the cache management function from the controller by introducing a separate cache controller that handles all cache-related operations. This includes allocating cache entries, managing replacement policies, and handling cache flush operations, thereby reducing the complexity of the main controller while maintaining high-speed cache performance.
Solution Approach 2:
The cache controller acts as an intermediary between the host and the cache memory. It receives commands from the host, manages cache allocation and replacement, and coordinates data transfer operations. This intermediary layer simplifies the main controller's workload while ensuring efficient cache utilization.
2Reliability
If capacitor is used as standby power, then data transfer during power outage is enabled, but the size of buffer memory is limited due to faster semiconductor technology advancements
Solution Approach 1:
The patent implements dynamic adjustment of the buffer memory size based on the available standby power capacity. The system can configure the buffer memory size to match the capacitor's energy capacity, allowing flexible adaptation to different power scenarios. This dynamic sizing ensures reliable data transfer during power outages while optimizing the use of available power resources.
Solution Approach 2:
The system changes the parameter of buffer memory size according to the standby power capacity. By adjusting this parameter dynamically, the system can maximize data transfer reliability during power outages without being constrained by fixed hardware limitations, allowing the buffer memory size to scale with available power resources.
3Ease of operation
If interrupt messages are sent for every write operation completion, then host control flexibility is improved, but power consumption increases and controller complexity increases
Solution Approach 1:
Instead of sending interrupt messages for every write operation completion, the system implements partial action by sending interrupts only when necessary (e.g., when buffer memory is full or when data has been flushed to non-volatile storage). This selective interrupt mechanism maintains host control flexibility for critical operations while significantly reducing unnecessary power consumption from continuous interrupt traffic.
Solution Approach 2:
The cache controller autonomously manages interrupt generation based on internal state conditions. It self-determines when interrupts are necessary and generates them accordingly, eliminating the need for continuous host-driven interrupt requests. This self-service approach reduces power consumption while maintaining operational flexibility.
Data Source
AI summary
A storage device includes a flash memory and a buffer memory. A method of controlling interrupts includes: receiving data to be written to the storage device from an information processing device; writing the received data to be written to the storage device to the buffer memory; fetching the data in the buffer memory and writing the data to the flash memory; in which, after writing the received data to be written to the storage device to the buffer memory, if the amount of data in the buffer memory is less than the predetermined threshold, then sending a message indicating the completion of the write operation to the information processing device.