Storage Device Logical Devices Parallel Memory Access
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Solution Overview
Problem
Existing storage devices face challenges in efficiently processing concurrent memory access requests from parallel computation workloads, leading to performance bottlenecks and increased latency.
Innovation Solution
The implementation of a method and system that utilize multiple logical devices within a storage device to process concurrent memory access requests in parallel. These logical devices are configured and allocated resources based on the bandwidth requirements of the memory requests, allowing for efficient handling of parallel computation workloads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logical devices are used to process concurrent memory access requests in parallel, then productivity is improved, but device complexity increases
Solution Approach 1:
The storage device is divided into multiple logical devices, each capable of independently processing memory access requests. This segmentation allows parallel processing of concurrent requests from parallel computation workloads, thereby improving productivity while managing complexity through modular organization
Solution Approach 2:
Each logical device is designed with multi-functionality to handle various types of memory access requests (read, write, erase) and can be dynamically configured based on workload requirements. This universality allows the system to maintain high productivity across different operation types without requiring specialized hardware for each function
2Productivity
If logical devices are configured based on bandwidth requirements, then memory access efficiency is improved, but ease of operation deteriorates
Solution Approach 1:
The logical devices are dynamically configured based on the bandwidth requirements of incoming memory access requests. The system can adjust the number and capacity of logical devices in real-time according to workload characteristics, optimizing memory access efficiency while abstracting the complexity from users through automated configuration management
3Loss of time
If parallel processing of memory access requests is implemented, then latency is reduced, but device complexity increases
Solution Approach 1:
The parallel processing architecture is segmented into multiple independent logical devices that can simultaneously handle different memory access requests. This segmentation reduces latency by enabling true parallel execution while managing complexity through clear separation of processing paths and resource allocation mechanisms
Data Source
AI summary
A method for memory access may include receiving, at a device, a first memory access request for a parallel workload, receiving, at the device, a second memory access request for the parallel workload, processing, by a first logical device of the device, the first memory access request, and processing, by a second logical device of the device, the second memory access request. Processing the first memory access request and processing the second memory access request may include parallel processing the first and second memory access requests. The first logical device may include one or more first resources. The method may further include configuring the first logical device based on one or more first parameters of the parallel workload. The method may further include allocating one or more first resources to the first logical device based on at least one of the one or more first parameters of the parallel workload.