Storage Device Memory Controller Namespace Segmentation

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Solution Overview

Problem

Existing storage devices lack flexibility and reliability in managing nonvolatile memory chips, particularly in integrating and accessing storage spaces across multiple chips, leading to inefficiencies and potential failures due to unbalanced wear and tear.

Innovation Solution

A method where a memory controller in a storage device manages and integrates storage spaces from multiple nonvolatile memory chips, allowing for both integration and individual modes of operation, dynamically adjusting namespace configurations and access based on host device requests, and updating configurations in response to failures to maintain performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If storage spaces from multiple nonvolatile memory chips are integrated into a single namespace, then storage access flexibility is improved, but reliability deteriorates due to unbalanced wear and tear across chips

Engineering Contradiction:

Improvestorage access flexibilityVSAvoidwear balance

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent divides the integrated storage space into multiple sub-areas corresponding to different nonvolatile memory chips. Each sub-area is managed independently with its own wear counter, allowing the system to segment the unified namespace into manageable portions that can be balanced individually to prevent uneven wear across chips.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically adjusts namespace configurations by changing parameters such as chip selection and access distribution based on wear levels. The system monitors wear counters and modifies namespace mappings to redirect operations to less worn chips, thereby maintaining reliability while preserving access flexibility.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If dynamic namespace configuration is implemented to respond to failures, then reliability is improved, but device complexity increases

Engineering Contradiction:

Improvefailure responseVSAvoidconfiguration management

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the memory controller continuously monitors the operational status of nonvolatile memory chips and dynamically adjusts namespace configurations in response to failures or performance degradation. This closed-loop system automatically redistributes storage operations to healthy chips, improving reliability while managing complexity through automated decision-making.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The system performs self-diagnosis and self-adjustment by monitoring chip health and automatically reconfiguring namespace mappings without external intervention. The memory controller independently detects failures and redistributes data access, reducing the need for complex external management while maintaining high reliability.

Inventive Principle:

Principle #25Self-service

3Quantity of substance

If multiple nonvolatile memory chips are used to increase storage capacity, then storage capacity is improved, but reliability deteriorates due to higher failure probability

Engineering Contradiction:

Improvestorage capacityVSAvoidsystem failure probability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent merges multiple nonvolatile memory chips into a unified storage system managed by a single namespace. This consolidation allows the system to present a unified interface to the host while internally distributing operations across multiple chips, thereby achieving increased capacity while maintaining reliability through coordinated management.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent strives to maintain equipotentiality in terms of wear distribution across all nonvolatile memory chips. By monitoring wear counters and dynamically balancing access patterns, the system ensures that all chips experience similar wear levels, preventing any single chip from becoming a weak point and thereby maintaining high reliability despite having multiple chips.

Inventive Principle:

Principle #12Equipotentiality

Data Source

PatentEP4053705B1Operating method of storage device

Publication Date: 2023.10.25 SAMSUNG ELECTRONICS CO LTD

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AI summary

Disclosed is an operating method of a storage device (100) which includes a plurality of nonvolatile memory chips (110). The method includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device (20), receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.