Storage Device Memory Profiling via Cache-Coherent Interconnect
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Solution Overview
Problem
Conventional general-purpose host processors are overwhelmed and unable to effectively perform memory profiling, placement, and migration operations in systems handling complex computational and memory-intensive workloads, such as those in AI, ML, and image processing, due to the large scale of memory spaces involved.
Innovation Solution
The introduction of storage devices with profiling and migrating engines that track and calculate access statistics for host-managed device memory, enabling external host processors to make memory allocation decisions without computational burdens, and manage memory migration or placement operations by providing access statistics and performing data migration within coherent memory spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If general-purpose host processors perform memory profiling, placement, and migration operations, then memory management functionality is provided, but the processors become overwhelmed and unable to effectively handle complex computational workloads
Solution Approach 1:
The patent extracts memory profiling, placement, and migration operations from the general-purpose host processor to dedicated storage devices. The host processor delegates these memory management tasks to storage devices equipped with profiling engines, allowing the processor to focus on computational workloads while the storage devices handle memory optimization independently.
Solution Approach 2:
The storage device acts as an intermediary between the host processor and device memory. It provides memory management services by profiling access patterns, calculating statistics, and performing placement/migration operations, thereby relieving the host processor of these computational burdens while maintaining efficient memory management.
2Measurement precision
If host processors calculate access statistics for memory optimization, then memory allocation decisions can be made, but the computational burden overwhelms the processors
Solution Approach 1:
The storage device performs self-service by automatically profiling memory access patterns and calculating statistics without requiring host processor intervention. The profiling engine within the storage device independently tracks reads and writes to device memory, computes access statistics, and uses this information for optimization decisions, eliminating the computational burden from the host processor.
Solution Approach 2:
The storage device serves as an intermediary that handles the computationally intensive task of calculating access statistics. It collects raw access data, processes it locally through its profiling engine, and provides optimized memory management services, thereby reducing the energy and computational resources required by the host processor.
3Productivity
If storage devices track and calculate access statistics for host-managed device memory, then memory profiling efficiency is improved, but device complexity increases
Solution Approach 1:
The storage device is designed with multi-functionality, serving both as a storage medium and as a memory management unit. By integrating a profiling engine that can track access patterns and calculate statistics, the storage device performs multiple functions (storage, profiling, optimization) within a single device, improving memory profiling efficiency without requiring separate dedicated hardware for each function.
Solution Approach 2:
The patent merges the memory profiling functionality with the storage device. The profiling engine is integrated into the storage device's architecture, combining storage operations with access pattern tracking and statistics calculation in a unified system, thereby improving efficiency while managing complexity through integration rather than separation of functions.
Data Source
AI summary
The disclosed computer-implemented method may include (1) receiving, at a storage device via a cache-coherent interconnect, a first request to access data at one or more host addresses of a coherent memory space of an external host processor, (2) updating, in response to the first request, one or more statistics associated with accessing the data at the one or more host addresses, (3) receiving, at the storage device via the cache-coherent interconnect, a second request to perform an operation associated with the one or more statistics, and (4) using the one or more statistics to perform the operation. Various other methods, systems, and computer-readable media are also disclosed.