Storage Device Parallel Reading Optimization via Address Conversion
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Solution Overview
Problem
Existing information processing devices and storage devices face inefficiencies in reading data from non-volatile memory, particularly due to non-parallel reading patterns that can lead to bottlenecks in data access and reduced performance.
Innovation Solution
An information processing device calculates an evaluation value for data storage locations using address conversion data to identify areas readable in parallel, relocating data to optimize parallel reading efficiency by distributing it across multiple physical addresses in the non-volatile memory, thereby improving reading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If data is stored in non-volatile memory, then data persistence is improved, but reading efficiency deteriorates due to non-parallel reading patterns
Solution Approach 1:
The patent segments data into multiple data groups and distributes them across different physical addresses in non-volatile memory. This segmentation enables parallel reading operations by organizing data so that multiple reading units can access different segments simultaneously, thereby improving reading efficiency while maintaining data persistence.
Solution Approach 2:
The patent introduces a new dimension of parallelism by utilizing multiple reading units that can operate simultaneously on different physical addresses. This dimensional expansion from sequential to parallel access transforms the reading operation, allowing multiple data groups to be read concurrently without compromising data persistence in non-volatile memory.
2Device complexity
If data is read sequentially from non-volatile memory, then system complexity is reduced, but reading speed deteriorates
Solution Approach 1:
The patent performs preliminary organization of data into multiple data groups assigned to different physical addresses before reading operations. This preliminary arrangement enables subsequent parallel reading without requiring complex real-time management during the reading process itself, thus maintaining relatively simple system complexity while achieving higher reading speeds through concurrent access.
3Productivity
If multiple reading units are used to improve parallelism, then reading performance is improved, but device complexity increases
Solution Approach 1:
The patent introduces an address conversion data structure as an intermediary that maps logical addresses to physical addresses across multiple reading units. This intermediary layer manages the complexity of coordinating multiple reading units by providing a standardized interface, allowing high reading performance through parallelism while keeping the control logic manageable through the address conversion mechanism.
Data Source
AI summary
According to one embodiment, an information processing device includes a processor configured to refer to address conversion data. The address conversion data has a plurality of logical addresses associated with a plurality of physical addresses of a storage device. The processor converts the plurality of logical addresses of an evaluation target in storage device into the corresponding plurality of physical addresses for the evaluation target by referring to the address conversion data. The processor then calculates an evaluation value indicating a parallel reading performance for the plurality of physical addresses of the evaluation target using a parameter specifying a number of areas of the storage device readable in parallel.