Semiconductor Storage Device Pattern Regions for Address Recognition
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Solution Overview
Problem
Current semiconductor storage devices face challenges in efficiently connecting and addressing memory blocks and bit lines due to limitations in pattern formation and representation on the chip surface, which hinders precise physical analysis and data storage efficiency.
Innovation Solution
The semiconductor storage device employs pattern regions on the chip surface, represented by conductive pattern members or holes, arranged in a binary or ternary format to indicate address positions of memory blocks and bit lines, allowing for precise physical analysis and improved data storage efficiency through unique pattern configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional pattern formation methods are used on the chip surface, then the device structure is simple, but the address recognition precision and physical analysis capability are insufficient
Solution Approach 1:
The chip surface is divided into multiple pattern regions, with each region containing patterns that represent specific address information for memory blocks and bit lines. This segmentation allows precise physical analysis and address recognition by dividing the addressing function across multiple spatially distributed pattern regions.
Solution Approach 2:
The patent introduces a new dimension of pattern formation on the chip surface, using conductive pattern members or holes arranged in binary or ternary formats. This adds a spatial dimension for encoding address information, enabling more precise address recognition beyond conventional methods.
2Manufacturing precision
If more pattern regions are added to represent address positions, then the address recognition accuracy improves, but the manufacturing complexity increases
Solution Approach 1:
The patent employs binary or ternary parameter systems for pattern representation, where pattern members or holes encode address information through their presence, absence, or configuration. This parameter-based approach enables precise address positioning while maintaining manufacturability through standardized pattern formation processes.
3Productivity
If conventional addressing methods are used, then the device structure is simple, but the data storage efficiency is limited
Solution Approach 1:
The pattern regions serve multiple functions: they provide physical analysis capabilities, encode address information for memory blocks and bit lines, and enable efficient data storage. This multi-functionality improves data storage efficiency by integrating addressing and storage functions into a unified structure.
Data Source
AI summary
According to one or more embodiments, a semiconductor storage device includes a first chip and a second chip. The first chip includes a semiconductor substrate and a plurality of transistors on the semiconductor substrate. The second chip includes a memory cell array and a plurality of first patterns. The memory cell array is connected to the plurality of transistors of the first chip and includes a plurality of memory blocks arranged in a first direction. The plurality of first patterns are spaced from each other in the first direction. Each first pattern represents a different number and is at a position corresponding to one or more of the memory blocks.