Storage Device Connection Checking via Training Command
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Solution Overview
Problem
In the semiconductor industry, there is a challenge in effectively checking the connection state between chips and printed circuit boards (PCBs) during packaging, which can lead to poor assembly and impede data transmission, requiring a method to efficiently verify connection integrity before training operations.
Innovation Solution
A storage device that utilizes a training command and pattern to check the connection state between chips by setting a lower frequency for the connection state checking operation, comparing pre-set and received training patterns to determine if the connection is poor, and using a connection checking module with a training pattern setting and frequency control module to facilitate this process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection state checking is performed using training commands during training operations, then connection integrity can be verified, but the complexity of the checking process increases
Solution Approach 1:
The patent performs connection state checking before the actual data transmission begins by utilizing training operations. The training pattern is transmitted through the connection being tested, and the received pattern is compared with the original to detect poor connections proactively, before they affect normal operation.
Solution Approach 2:
The patent implements a feedback mechanism where the training pattern received at the destination is compared with the originally transmitted training pattern. This feedback loop enables detection of connection degradation, and the system can respond by adjusting training patterns or flagging connection issues for further investigation.
2Productivity
If training operations are used for both training and connection checking, then resource utilization improves, but the precision of connection state detection may be compromised
Solution Approach 1:
The patent segments the training operation into two distinct phases: a training phase where the training pattern is transmitted through the connection being tested, and a checking phase where the received pattern is compared with the original. This segmentation allows the same training infrastructure to serve dual purposes while maintaining detection accuracy through systematic comparison.
Solution Approach 2:
The patent changes the parameter of data transmission by using training patterns with specific characteristics (such as predetermined sequences like 0x55 or 0xAA) that are optimized for detecting connection issues. These special training patterns are designed to expose connection problems that normal data transmission might not reveal.
3Speed
If connection checking is performed at high frequency, then data transmission speed is maintained, but the time for connection state analysis increases
Solution Approach 1:
The patent performs connection state checking during the training operation phase, which occurs before normal high-speed data transmission begins. By completing the checking action in advance during the training phase, the system avoids interrupting or slowing down subsequent high-speed data transmission operations.
Solution Approach 2:
The patent implements periodic connection checking during training operations at lower frequencies, allowing the system to maintain connection integrity verification without continuously impacting data transmission speed. The checking occurs at appropriate intervals during the training sequence rather than continuously during high-speed operation.
Data Source
AI summary
A storage device may include a first chip and a second chip connected to the first chip and configured to exchange a plurality of data signals with the first chip. The first chip and the second chip may align the plurality of data signals using a training command during a training operation, and the first chip and the second chip may check whether a connection state between data input/output pins of the first chip and data input/output pins of the second chip is poor, by utilizing the training command, during a connection state checking operation.