Storage Device Read Voltage Adjustment for Erased Sub-Blocks
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Solution Overview
Problem
Three-dimensional structured storage devices face challenges in maintaining reliable read operations due to variations in channel resistance caused by erased sub-blocks, leading to decreased electrical characteristics.
Innovation Solution
The solution involves adjusting operation voltages based on the presence of erased sub-blocks within a memory block, lowering specific voltage levels to compensate for reduced channel resistance and improve read operation reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read operation is performed using standard operation voltages, then read speed is maintained, but read reliability deteriorates when erased sub-blocks are present due to channel resistance variations
Solution Approach 1:
The patent applies dynamics by making the operation voltages adjustable rather than fixed. The control logic dynamically selects between first operation voltages (for blocks without erased sub-blocks) and second operation voltages (for blocks with erased sub-blocks), allowing the system to adapt voltage levels based on the actual state of the memory block being read, thereby improving read reliability without excessive complexity
Solution Approach 2:
The patent changes the voltage parameter based on the presence of erased sub-blocks. By switching between different voltage levels (first operation voltages vs. second operation voltages) depending on the block state, the system compensates for channel resistance variations caused by erased sub-blocks, resolving the contradiction between maintaining standard read performance and ensuring reliable reads in all conditions
2Reliability
If operation voltages are lowered to compensate for erased sub-blocks, then read reliability improves, but read speed may deteriorate
Solution Approach 1:
The patent changes voltage parameters conditionally rather than uniformly. By applying lower second operation voltages only when erased sub-blocks are detected and maintaining first operation voltages when they are not present, the system improves reliability where needed while preserving read speed in normal conditions, thus resolving the speed-reliability trade-off
3Reliability
If uniform read operation is used across all sub-blocks, then operation simplicity is maintained, but electrical characteristics deteriorate due to channel resistance variations from erased sub-blocks
Solution Approach 1:
The patent applies local quality by differentiating the read operation based on the local state of each memory block. Instead of applying a uniform read operation to all blocks, the control logic identifies blocks containing erased sub-blocks and applies specific second operation voltages to those local regions, while using first operation voltages for other blocks, thereby improving electrical characteristics where needed without complicating the overall system
Data Source
AI summary
There are provided a storage device and an operating method thereof. A storage device includes a main block including a plurality of sub-blocks, a peripheral circuit for generating operation voltages used in a read operation of a selected sub-block among the sub-blocks and performing the read operation of the selected sub-block by using the operation voltages, and a control logic for, when an erased sub-block among the sub-blocks is included in the read operation, controlling the peripheral circuit to perform the read operation by lowering levels of some of the operation voltages.