Storage Device Write Enable Bit Pattern Matching
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Solution Overview
Problem
Existing storage devices face inefficiencies in write processing, as they often require sequential writing of data packets, leading to increased processing time and potential errors in distinguishing between intended and unintended data errors, and require additional bits for error detection and skip judgment, increasing data packet size.
Innovation Solution
A storage device with a control unit that determines write instructions based on a specific data pattern between write data and additional data, allowing for efficient data configuration by skipping write processing when the pattern matches, and using additional data for error checking and judgment, thereby reducing processing time and packet size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the storage device sequentially writes all received data packets including those that need not be written, then all data is preserved, but the write time greatly increases
Solution Approach 1:
The host device performs preliminary action by setting the write enable bit WE to inhibit writing in advance before transmitting data packets that need not be written. This allows the storage device to skip write processing for these packets without risking data loss, as the host has already determined which packets should be skipped. The address is still updated to maintain sequential address allocation, while the write operation is prevented by the pre-set WE bit.
2Loss of time
If the host device transmits feeding coded data with errors to indicate skip writing, then write processing is omitted, but the storage device cannot distinguish between actual errors and intentional skip signals
Solution Approach 1:
The write enable bit WE serves as an intermediary signal between the host device and storage device. Instead of using error-coded data to indicate skip writing, the host sets the WE bit to a specific value (inhibiting writing) as a clear, unambiguous intermediate signal. This mediator bit allows the storage device to reliably distinguish between actual data errors (which would affect data integrity) and intentional skip instructions (indicated by WE), eliminating confusion while enabling write processing omission.
3Ease of operation
If the host device includes the write enable bit WE in data packets, then skip writing is controlled, but the data packet size increases or the write data size decreases
Solution Approach 1:
The write enable bit WE is integrated into the existing data packet structure as a multi-functional element. It serves dual purposes: controlling whether writing should be skipped and maintaining compatibility with standard data packet formats. By making the WE bit a universal component of the data packet rather than an add-on, the system achieves skip writing control without significantly increasing overall packet size, as the bit is incorporated into the existing transmission framework.
Data Source
AI summary
Provided is a storage device, a liquid container and a host device that appropriately control whether or not writing is to be performed with an efficient data configuration.The storage device 100 includes a control unit 110 that performs processing for communication with a host device 400, a storage unit 120, and a storage control unit 130 that performs access control on the storage unit 120. The control unit 110 receives a write data packet from the host device 400, and if a data pattern of write data included in the write data packet and additional data is judged as not matching a specific pattern, makes update instruction of address information and write instruction regarding write data to the storage control unit 130. If judged as matching, the control unit 110 does not make a write instruction regarding the write data, while making an update instruction of the address information.