Storage System Direct Cache Write for NVMe Reliability

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Solution Overview

Problem

In storage systems using NVMe, the lack of SAS protocol control leads to unreliable data transfer and increased memory bandwidth consumption due to redundant data writing during read processing, hindering speed and reliability.

Innovation Solution

A storage system configuration that includes a first arithmetic unit for input/output processing, a first memory, multiple storage drives, a second arithmetic unit, and a second memory, where the first unit instructs the drives to read data into the second memory, which is then stored and transmitted to the request source, preventing redundant writing and ensuring high reliability and speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data is written to buffer area and then to cache area in read processing, then data transfer reliability is improved, but memory bandwidth consumption increases and transfer speed decreases

Engineering Contradiction:
Improvedata transfer reliabilityVSAvoiddata transfer speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent extracts the redundant buffer writing step from the traditional data transfer path. Instead of writing data from storage drive to buffer area and then to cache area, the system directly writes data from the storage drive to the cache area, eliminating the unnecessary intermediate buffer writing operation while maintaining data reliability through direct controller management.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs preliminary allocation of cache area memory addresses by the controller before data transfer. The controller pre-allocates memory addresses in the cache area and provides these addresses to the storage drive, enabling direct writing of data to the cache area without requiring intermediate buffer processing, thus improving transfer efficiency.

Inventive Principle:
Principle #10Preliminary action

2Speed

If NVMe protocol is used without SAS protocol control, then processing speed is improved, but data transfer reliability deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoiddata transfer reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The controller serves as an intermediary between the storage drive and the host system. It receives data directly from the storage drive into the cache area, manages data integrity through error checking and correction functions, and then transmits verified data to the host. This intermediary role maintains the high-speed NVMe protocol benefits while ensuring data reliability through centralized controller management.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system implements feedback mechanisms where the controller monitors data transfer processes, performs error detection and correction, and manages cache area allocations dynamically. This feedback control ensures data reliability while maintaining high processing speeds by quickly identifying and correcting errors without requiring redundant writing operations.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11740799B2Storage system and input and output control method
Publication Date: 2023.08.29 HITACHI VANTARA LTD
  • US11740799B2 patent drawing
  • US11740799B2 patent drawing
  • US11740799B2 patent drawing

AI summary

A storage system having high reliability and IO processing performance is realized. The storage system includes: a first arithmetic unit configured to receive an input and output request and perform data input and output processing; a first memory connected to the first arithmetic unit; a plurality of storage drives configured to store data; a second arithmetic unit; and a second memory connected to the second arithmetic unit. The first arithmetic unit instructs the storage drive to read data, the storage drive reads the data and stores the data in the second memory, the second arithmetic unit stores the data stored in the second memory in the first memory, and the first arithmetic unit transmits the data stored in the first memory to a request source of a read request for the data.