Storage Controller Driver Reinitialization via Segmented Quiesce Periods
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Solution Overview
Problem
In storage controllers, existing technologies face challenges in efficiently and minimally disrupting host I/O operations during recovery from logic errors, requiring timely resets without noticeable increases in response times.
Innovation Solution
A driver for a host bus adapter performs hardware resets and reinitialization in two quiesce periods, using application programming interfaces to manage I/O operations, restore configuration spaces, and resume normal operations with minimal impact on active host I/O.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a storage controller performs hardware resets and reinitialization to recover from logic errors, then reliability is improved, but host I/O operations are disrupted and response time increases
Solution Approach 1:
The patent segments the reinitialization process into two distinct phases: a first quiesce period for hardware resets and a second quiesce period for driver reinitialization. This segmentation allows the system to perform comprehensive recovery operations while minimizing the overall impact on host I/O operations by spreading the quiescing events across different time intervals.
Solution Approach 2:
The patent applies preliminary action by transmitting commands to quiesce I/O operations before performing hardware resets and driver reinitialization. By proactively stopping I/O operations in advance, the system prepares the storage controller for reinitialization, ensuring that recovery operations can proceed without interference from active I/O, thereby reducing the overall impact on response time.
2Reliability
If a storage controller performs comprehensive hardware resets and driver reinitialization, then reliability is improved, but the complexity of the reinitialization process increases
Solution Approach 1:
The patent divides the complex reinitialization process into manageable segments: (1) first quiesce period for hardware resets, (2) restoration of configuration spaces, and (3) second quiesce period for driver reinitialization. Each segment has a specific purpose and can be independently managed, reducing the overall complexity of the recovery process.
Solution Approach 2:
The patent employs periodic action by using two distinct quiesce periods separated by intermediate operations. The first quiesce period is followed by configuration restoration, then a second quiesce period is used for driver reinitialization. This periodic structure organizes the complex reinitialization process into repeatable, manageable cycles.
3Loss of time
If a storage controller minimizes quiesce periods for rapid recovery, then response time is improved, but the completeness of reinitialization may be compromised
Solution Approach 1:
The patent segments the reinitialization into two quiesce periods with intermediate operations, allowing comprehensive recovery to be completed across multiple shorter intervals rather than requiring one long quiesce period. This segmentation enables the system to achieve complete reinitialization while minimizing the total time impact on host I/O operations.
Solution Approach 2:
The patent maintains continuity of useful action by performing configuration space restoration during the interval between the two quiesce periods. While the system is in the intermediate state after the first quiesce period, essential restoration operations continue, ensuring that the overall reinitialization process remains continuous and complete without requiring extended quiescing.
Data Source
AI summary
A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is connected, in a first period of quiescing of I/O operations in the embedded port. The driver transmits one or more commands to the embedded port to resume selected I/O operations in the embedded port. A reinitialization of the driver is performed during a second period of quiescing of I/O operations in the embedded port, prior to sending a command to allow normal I/O operations in the embedded port.


