Storage ECC Switching With Joint Parity for Low-Latency Reliability
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Solution Overview
Problem
Existing storage devices face challenges in achieving fast read and write speeds while maintaining data retention and reliability, particularly due to high bit error rates and the need for multiple memory types, which increases fabrication costs and latency.
Innovation Solution
A data storage device that varies parity size using error correcting codes, transitioning between short and long codes to match volatile and non-volatile memory requirements, and generates joint parity information to enhance error correction capability, allowing for efficient operation across both memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a strong ECC scheme is used to compensate for high BER in universal memory, then reliability is improved, but latency increases
Solution Approach 1:
The patent implements dynamic ECC scheme selection that adapts to different operational modes (volatile vs. non-volatile). The system transitions between short ECC codes for fast operations and long ECC codes for reliable non-volatile storage, making the error correction capability flexible rather than static. This resolves the contradiction by applying strong ECC only when needed for non-volatile operations.
Solution Approach 2:
The system changes the parameters of the ECC scheme based on operational requirements. It uses code rate adjustment and code length variation to balance between error correction strength and processing speed. By modifying ECC parameters dynamically, the system achieves both low latency when possible and high reliability when required.
2Reliability
If multiple memory types (DRAM and flash) are used to achieve fast read/write with data retention, then performance is improved, but fabrication cost increases
Solution Approach 1:
The patent employs a universal memory device that can function in both volatile and non-volatile modes, eliminating the need for separate DRAM and flash memory components. This multi-functional approach reduces fabrication costs by using a single memory type while maintaining data retention capability through mode switching and appropriate ECC schemes.
Solution Approach 2:
The invention extracts and removes one of the memory types from the hybrid architecture. By using universal memory with enhanced ECC capabilities, the system eliminates the need for dual memory types, thereby reducing manufacturing complexity and cost while preserving the essential functions of both volatile and non-volatile storage.
3Speed
If multiple memory types are used to achieve fast read/write speeds, then speed is improved, but device complexity increases
Solution Approach 1:
The system uses a universal memory device that can operate in different modes (volatile and non-volatile) to provide fast read/write speeds. This approach simplifies the overall architecture by replacing complex multi-memory-type systems with a single versatile memory component that adapts its behavior based on operational requirements.
Solution Approach 2:
The patent implements dynamic mode switching between volatile and non-volatile operations within a single memory device. This dynamic behavior allows the system to achieve fast speeds when in volatile mode while maintaining data retention when in non-volatile mode, all within a simplified single-memory architecture rather than complex multi-memory systems.
Data Source
AI summary
A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.