Storage Error Identification Engine for Flash Memory

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Solution Overview

Problem

Information handling systems face challenges in identifying and reducing errors in flash-based storage subsystems due to changing health characteristics, which lead to uncorrectable errors and require time-intensive data recovery techniques, as existing methods cannot distinguish between temporary and physical effects causing errors.

Innovation Solution

An Information Handling System (IHS) with a storage error identification/reduction engine that writes storage error identification data with predetermined values to adjacent locations, reads this data to identify errors, and performs error reduction operations based on the identified errors, allowing for targeted correction and minimization of errors during data retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage level shifting operations are conducted based on best guess with repeated iterations to reduce errors, then error reduction may be achieved, but time consumption and processing overhead increase significantly

Engineering Contradiction:
Improveerror reductionVSAvoidtime consumption
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by writing storage error identification data with predetermined values to adjacent storage locations before actual data storage. This allows error identification to be performed in advance, determining the relationship between adjacent storage locations and error characteristics before data retrieval, thereby avoiding time-consuming iterative voltage level shifting during data access operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces storage error identification data as an intermediary element with predetermined values written to adjacent storage locations. This intermediary data serves as a reference to identify errors and determine voltage level shifting relationships without requiring direct manipulation of the actual stored data, thus reducing processing time while maintaining error reduction effectiveness.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data is moved to new storage locations to refresh and reset temporary effects, then error reduction is achieved, but processing intensity and time requirements increase

Engineering Contradiction:
Improveerror reductionVSAvoidprocessing intensity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary error identification by reading storage error identification data from adjacent storage locations before data movement operations. This preliminary action determines the error characteristics and voltage level relationships in advance, allowing the system to selectively move only necessary data blocks and avoid unnecessary processing, thereby reducing overall processing intensity while maintaining error reduction benefits.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using the identified error characteristics from storage error identification data to guide subsequent data movement and voltage level adjustment decisions. The system continuously monitors error patterns and adjusts its operations accordingly, moving data only when and where necessary to address identified errors, thus optimizing productivity while maintaining reliability.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If comprehensive error analysis is performed to distinguish between physical and temporary effects, then error identification accuracy improves, but system complexity and processing overhead increase

Engineering Contradiction:
Improveerror identification accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by focusing error identification efforts on adjacent storage locations where errors are most likely to occur due to physical proximity and shared circuitry. By concentrating analysis on these specific local areas rather than performing comprehensive system-wide analysis, the patent achieves high error identification accuracy while minimizing system complexity and processing overhead.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent uses storage error identification data as a simplified copy or model of the actual storage characteristics in adjacent locations. This copying approach allows the system to analyze error patterns and voltage level relationships without directly examining and analyzing every stored data block, thereby achieving accurate error identification while keeping system complexity manageable.

Inventive Principle:
Principle #26Copying

Data Source

PatentUS11966277B2Storage error identification/reduction system
Publication Date: 2024.04.23 DELL PROD LP
  • US11966277B2 patent drawing
  • US11966277B2 patent drawing
  • US11966277B2 patent drawing

AI summary

A storage error identification/reduction system includes a storage error identification/reduction subsystem coupled to a storage subsystem including a block. The storage error identification/reduction subsystem receives first data, and writes the first data to first storage locations in the block while writing storage error identification data to second storage location(s) in the block that each are located adjacent at least one of the first storage locations, with the storage error identification data including predetermined values that are written to predetermined locations included in the second storage location(s) in the block. The storage error identification/reduction subsystem then reads the storage error identification data from the second storage location(s) and, based on the predetermined values and predetermined locations of the storage error identification data, identifies errors resulting from the reading of the storage error identification data. Based on the errors, the storage error identification/reduction subsystem determines and performs error reduction operation(s).