Storage Integrity Hash Mapping for Small-Buffer Write Verification

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Solution Overview

Problem

The increasing data capacity sent to storage devices from host devices exceeds the storage capacity of buffer memories in storage devices, leading to insufficient data integrity verification and potential increases in manufacturing costs and latency.

Innovation Solution

A storage system with a host device and storage device that performs data integrity verification using an integrity hash map stored in a buffer memory with a capacity smaller than the data chunk, allowing parallel data integrity verification and writing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the buffer memory storage capacity is increased to match the data chunk size for data integrity verification, then data integrity verification can be performed, but manufacturing costs and device complexity increase

Engineering Contradiction:
Improvedata integrity verificationVSAvoidmanufacturing cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The data chunk is divided into multiple write data units, and the integrity hash map stores verification information for each unit separately. This segmentation allows the buffer memory to store only essential verification data rather than the entire data chunk, reducing storage capacity requirements while maintaining data integrity verification capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts only the essential verification information (integrity hash values) from the complete data chunk and stores it in the buffer memory. This extraction approach allows data integrity verification to be performed using a small buffer memory without needing to store the entire data chunk, thereby reducing manufacturing costs

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If the buffer memory storage capacity is increased to match the data chunk size, then data integrity verification can be performed, but device complexity and latency increase

Engineering Contradiction:
Improvedata integrity verificationVSAvoidbuffer memory size
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The integrity hash map is organized as a separate data structure that segments verification information from the main data chunk. This segmentation enables the buffer memory to be much smaller than the data chunk while still containing all necessary verification data, thereby reducing device complexity

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of storing the entire data chunk in the buffer memory, the patent creates a compact copy containing only the essential integrity hash values. This copied verification information is sufficient for data integrity verification, significantly reducing the buffer memory size and device complexity

Inventive Principle:
Principle #26Copying

3Reliability

If data integrity verification is performed sequentially after data writing, then verification accuracy is maintained, but processing latency increases

Engineering Contradiction:
Improvedata integrity verification accuracyVSAvoidprocessing latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The integrity hash values are calculated and stored in the integrity hash map during the data writing process itself, before the actual verification is needed. This preliminary action allows the verification phase to proceed quickly by simply comparing pre-computed hash values, thereby maintaining verification accuracy while reducing processing latency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous data writing and verification operations by maintaining the integrity hash map in the buffer memory. The verification process can continuously check incoming write data against the stored hash values without interrupting the data flow, ensuring both verification accuracy and minimal latency

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20260080103A1Storage system including host device and storage device, operation method thereof and operation method of storage device
Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD
  • US20260080103A1 patent drawing
  • US20260080103A1 patent drawing
  • US20260080103A1 patent drawing

AI summary

An operation method of a storage device includes receiving first and second write data from an external host device, the first and second write data among a plurality of write data included in a first chunk, generating first verification sub-hash data and second verification sub-hash data respectively corresponding to the first write data and the second write data, updating an integrity hash map by storing the first verification sub-hash data and the second verification sub-hash data in the integrity hash map, and performing data integrity verification for the plurality of write data, based on the integrity hash map completed. The storage device includes a buffer memory configured to store the integrity hash map and having a storage capacity smaller than a data size of the first chunk.