Storage Device HMB Access via Address Mapping Table

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Solution Overview

Problem

The existing methods for accessing Host Memory Buffer (HMB) in storage devices are inefficient, leading to high access latency and inconsistent performance, especially when the HMB space is large or the number of storage blocks is significant, due to the complexity of traversing the Host Memory Descriptor List (HMBDL) and Scatter-Gather List (SGL).

Innovation Solution

A method is introduced to rapidly access the HMB by establishing a mapping table that directly maps the control unit's address space to the host address space, reducing the need for traversing the HMBDL and SGL, and optimizing data transmission through the use of host space descriptors and DTU descriptors to facilitate efficient data processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If the Host Memory Descriptor List (HMBDL) and Scatter-Gather List (SGL) are traversed to access Host Memory Buffer (HMB), then the data can be located, but the access latency increases and performance becomes inconsistent

Engineering Contradiction:

Improveaccess latencyVSAvoidtraversal complexity

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

The patent pre-calculates and stores the mapping relationship between control unit address space and host address space in a mapping table before actual data access. This preliminary action eliminates the need for traversing HMBDL and SGL during runtime, directly reducing access latency while maintaining data location accuracy.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a mapping table as an intermediary structure that directly maps control unit address space to host address space. This intermediary eliminates the complex traversal process through HMBDL and SGL, providing a direct path for address conversion and improving access performance consistency.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If a mapping table is established to directly map control unit address space to host address space, then access efficiency improves and latency reduces, but the device complexity increases

Engineering Contradiction:

Improveaccess efficiencyVSAvoidmapping table structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the address space mapping into discrete mapping table entries, where each entry corresponds to a specific address range. This segmentation allows the mapping table to be built incrementally and queried efficiently, improving access efficiency while managing the complexity through structured organization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter representation from traversing multiple list structures (HMBDL, SGL) to direct address-based indexing in the mapping table. This parameter change transforms the access pattern from linear traversal to constant-time lookup, significantly improving productivity while the mapping table structure manages the complexity.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11650736B2SGL processing acceleration method and storage device

Publication Date: 2023.05.16 SHANGHAI STARBLAZE IND CO LTD

AI summary

Disclosed are the SGL processing acceleration method and the storage device. The disclosed SGL processing acceleration method includes: obtaining the SGL associated with the IO command; generating the host space descriptor list and the DTU descriptor list according to the SGL; obtaining one or more host space descriptors of the host space descriptor list according to the DTU descriptor of the DTU descriptor list; and initiating the data transmission according to the obtained one or more host space descriptors.