Storage Interface Compression for Faster Internal Memory Transfer
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Solution Overview
Problem
Storage systems with multiple memory devices face inefficiencies in internal data transmission speeds due to high traffic on internal communication interfaces, leading to lost clock cycles and reduced performance.
Innovation Solution
Implementing data compression by device controllers prior to transfer over internal communication interfaces to reduce traffic and enhance transmission speeds without increasing clock speed or capacity, using lossless compression algorithms and omitting padded bits to maintain alignment and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted uncompressed over internal communication interfaces, then data transmission capacity is maintained, but transmission speed decreases due to high traffic and lost clock cycles
Solution Approach 1:
The patent extracts and removes padded bits from data transmissions over the internal communication interface. Device controllers identify and omit trailing padded bits (e.g., zero bits) that do not carry meaningful information, thereby reducing the number of clock cycles required for transmission and improving effective data transmission speed without affecting data integrity.
Solution Approach 2:
The patent changes the parameter of data representation by transmitting data in a compressed format that eliminates redundant padded bits. The device controllers modify the transmission parameters by adjusting the data length based on actual data content rather than fixed alignment boundaries, reducing transmission time and improving speed.
2Productivity
If data compression is implemented by device controllers, then traffic on internal interfaces is reduced and transmission speed increases, but device complexity increases
Solution Approach 1:
The patent implements self-service by enabling device controllers to autonomously identify, compress, and transmit data without padded bits. The controllers independently determine the actual data length, remove redundant padding, and manage the compression process without requiring external intervention from the host system or memory controller, thereby improving efficiency while keeping the added complexity localized to individual device controllers.
3Speed
If padded bits are omitted from transmissions, then transmission speed improves, but data alignment and integrity requirements become more stringent
Solution Approach 1:
The patent implements feedback mechanisms where device controllers track and communicate the actual data length and alignment requirements to the memory controller. The memory controller uses this feedback information to properly interpret and process the compressed data transmissions, ensuring data integrity and correct alignment without requiring padded bits, thereby maintaining reliability while improving speed.
Data Source
AI summary
Apparatus and methods are disclosed, including enabling communication between a memory controller and multiple memory devices of a storage system using a storage-system interface, the multiple memory devices each comprising a device controller and a group of non-volatile memory cells, and compressing data using at least one of the device controllers prior to transfer over the storage-system interface to improve an effective internal data transmission speed of the storage system.