Storage Interface Circuit Pre-Emphasis Using Delay-Locked Loop Control
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Solution Overview
Problem
As data storage apparatuses increase in capacity and speed, existing interface circuits face challenges in accurately and efficiently generating signals for multiple input/output circuits, leading to potential signal attenuation and noise effects, which can compromise data integrity.
Innovation Solution
The implementation of a delay-locked loop circuit generates a delay code to create an additional signal for pre-emphasis, combined with transmission signals, within the interface circuit, allowing for precise delay control without the need for additional circuits, thereby enhancing area efficiency and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional circuits are added to generate delay codes for pre-emphasis signals, then signal integrity is improved, but device area increases
Solution Approach 1:
The delay-locked loop circuit is designed to perform multiple functions: it generates the delay code for pre-emphasis signal generation while also providing clock signal distribution and synchronization. This multi-functionality eliminates the need for separate delay circuitry, thereby maintaining signal integrity without increasing device area.
Solution Approach 2:
The invention merges the delay code generation function into the existing delay-locked loop circuit that is already present for clock synchronization. By combining these functions, the patent avoids adding separate circuits while still achieving the necessary delay control for pre-emphasis signal generation.
2Reliability
If delay control precision is increased to prevent signal attenuation, then data integrity is improved, but circuit complexity increases
Solution Approach 1:
The delay-locked loop circuit automatically generates the required delay code through its inherent feedback mechanism. The circuit self-adjusts to achieve precise delay control without requiring external control logic or additional complexity, thereby maintaining data integrity while avoiding increased circuit complexity.
Solution Approach 2:
The invention utilizes the delay-locked loop's ability to dynamically adjust delay parameters based on feedback from the clock signal. This parameter adjustment capability allows precise delay control for pre-emphasis without requiring complex fixed delay circuits, thus improving data integrity without significantly increasing circuit complexity.
Data Source
AI summary
A data storage apparatus is provided to include a memory device including memory cells for storing data; and an interface circuit coupled as an interface between the host device and the memory device and configured to transmit a transmission signal to the host. The interface circuit includes a delay circuit configured to generate a delay code and is configured to generate an additional signal to be combined with the transmission signal based on the delay code.