Storage I/O Dispatch Layer Path Selection via Pre-computed Caching
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Solution Overview
Problem
Traditional multipathing algorithms for storage I/O operations in low latency storage area networks, such as all-Flash storage arrays, incur substantial latency due to complex synchronization mechanisms and iterative evaluations of path statistics, which hinder performance.
Innovation Solution
An I/O dispatch layer that pre-picks the best Initiator-Target-LUN nexus based on periodic evaluation by a daemon thread, using private counters and simple lookups to minimize dispatch time and reduce locking overhead, thereby avoiding the need for complex synchronization and iterative evaluations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional multipathing algorithms evaluate counters on every I/O to pick the best path, then path selection accuracy is improved, but I/O dispatch latency increases substantially
Solution Approach 1:
The patent pre-calculates and stores the best path selection in a cache before I/O operations occur. The load balancer periodically evaluates path statistics and determines optimal paths in advance, storing these decisions in a cache that the I/O dispatcher can quickly retrieve without performing real-time evaluations during actual I/O operations.
Solution Approach 2:
The load balancer performs path evaluation and cache updates periodically rather than continuously for every I/O operation. This periodic evaluation maintains path selection accuracy while significantly reducing the frequency of complex counter evaluations, thereby lowering overall I/O dispatch latency.
2Measurement precision
If aggregate counters for I-T nexuses are derived by considering all I-T-L nexuses, then load balancing accuracy is improved, but synchronization complexity and locking overhead increase
Solution Approach 1:
The patent segments the counter evaluation process by maintaining separate counters for each I-T-L nexus while using hierarchical aggregation only for cache updates. Each I-T-L nexus maintains its own dispatch and completion counters independently, and the load balancer aggregates these for cache purposes without requiring synchronization during I/O operations.
Solution Approach 2:
The load balancer acts as an intermediary that periodically aggregates I-T-L counter data and updates the I-T nexus cache. This intermediary role separates the detailed counter maintenance at the I-T-L level from the aggregate load balancing decisions at the I-T level, reducing synchronization requirements.
3Measurement precision
If iterative evaluations of individual I-T-L nexuses are performed in dispatch context, then optimal path selection is improved, but dispatch time increases due to looping through all paths
Solution Approach 1:
The optimal path selection is performed in advance by the load balancer and stored in the cache before I/O operations need to be dispatched. This preliminary calculation eliminates the need for iterative evaluations during the actual dispatch process, allowing O(1) lookup time for path selection.
Solution Approach 2:
The patent creates a cached copy of the optimal path selection decisions that can be quickly referenced during I/O operations. Instead of performing full iterative evaluations of all I-T-L nexuses during dispatch, the system uses pre-computed cache entries that replicate the results of detailed evaluations without requiring the computational overhead.
Data Source
AI summary
A host computer dispatches storage I/O operations to a storage array by, in an I/O dispatch context, (i) identifying an I-T-L nexus based on a minimum-weight I-T nexus and a logical device of a storage I/O operation, (ii) dispatching the I/O on the identified I-T-L nexus, and (iii) updating a dispatch weight for the minimum-weight I-T nexus and logical device. In an I/O completion context, a completion weight is updated for an I-T nexus and logical device of a completed I/O. A background process is performed regularly for selecting the minimum-weight I-T nexus, including (a) for each I-T nexus, calculating a current weight value as a sum of difference values for all logical devices, each being the difference between the dispatch weight and the completion weight for the I-T nexus and logical device, and (b) selecting the I-T nexus having a minimum current weight value as the minimum-weight I-T nexus.