Storage Controller Latency Circuit for Workload-Independent Spike Prediction

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Solution Overview

Problem

Existing storage systems face challenges in accurately predicting latency spikes due to varying and complex host workloads, leading to inefficiencies in data management.

Innovation Solution

A storage controller with a latency calculation circuit that calculates latency based on time points of command division and execution within internal processing units, allowing for independent prediction of latency spikes without being influenced by host workload complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If latency prediction is based on host workload complexity, then prediction accuracy may be affected by varying workloads, but the system can handle diverse host requirements

Engineering Contradiction:
Improvelatency prediction accuracyVSAvoidhost workload complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the latency prediction function by separating internal storage device latency from host workload factors. The latency calculation circuit independently measures internal processing latency by timing command execution from receipt to completion notification, isolating this measurement from the complex and varying host workload conditions. This segmentation allows accurate internal latency prediction without being influenced by host workload complexity.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If the storage controller independently calculates internal latency, then latency prediction accuracy improves, but the device complexity increases due to additional circuitry

Engineering Contradiction:
Improveinternal latency prediction accuracyVSAvoidstorage controller structure
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The latency calculation circuit is merged into the existing storage controller structure, sharing resources with the command processing unit. The circuit utilizes the same command reception and completion notification mechanisms already present in the controller, adding timing measurement functionality without requiring completely separate hardware systems. This integration achieves independent latency calculation while minimizing additional device complexity.

Inventive Principle:
Principle #5Merging (Combining)

3Productivity

If latency threshold monitoring is implemented, then system performance optimization improves, but the ease of operation decreases due to additional configuration requirements

Engineering Contradiction:
Improvestorage system efficiencyVSAvoidlatency threshold configuration
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The latency calculation circuit automatically monitors and compares calculated latency values against threshold values without requiring manual intervention. The circuit self-manages the latency measurement, calculation, and threshold comparison processes, enabling storage system efficiency optimization through automated latency threshold monitoring that reduces operational complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12524182B2Storage device, storage controller and operating method of storage controller
Publication Date: 2026.01.13 SAMSUNG ELECTRONICS CO LTD
  • US12524182B2 patent drawing
  • US12524182B2 patent drawing
  • US12524182B2 patent drawing

AI summary

Provided is an operating method of a storage controller. The method includes fetching, by a processor, a command for a non-volatile memory received from a host, dividing, by the processor, the command into internal processing units, transmitting, by the processor, a first time point at which the command is divided into internal processing units to a latency calculation circuit, executing, by the processor, the command of an internal processing unit to a memory, transmitting, by the processor, a second time point at which the command of an internal processing unit is executed to the latency calculation circuit, calculating, by the latency calculation circuit, latency for the command based on the received first time point and the received second time point, and determining, by the latency calculation circuit, whether the calculated latency exceeds a preset threshold latency.