Semiconductor Storage Layer Structure for ON/OFF Current Control
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Solution Overview
Problem
Current semiconductor storage devices face challenges in manufacturing efficient memory dies with optimal semiconductor layer thickness and structure, leading to variations in ON and OFF currents, which affect performance and yield.
Innovation Solution
The semiconductor storage device comprises a substrate with conductive layers, insulating layers, and semiconductor layers, featuring specific thickness variations and regions, along with a gate insulating film, and a manufacturing method involving alternating layer formation, via hole creation, and oxidation treatment to achieve precise semiconductor layer thickness and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing methods are used, then manufacturing process is simple, but manufacturing precision of semiconductor layer thickness is insufficient
Solution Approach 1:
The patent employs preliminary action by forming a preliminary semiconductor layer with a first thickness, then performing selective removal to create the final non-uniform thickness profile. The manufacturing process includes: forming a preliminary semiconductor layer, performing first removal processing to remove part of the preliminary semiconductor layer, and performing second removal processing to remove another part. This preliminary formation followed by selective removal allows precise control of the final semiconductor layer thickness in different regions, achieving high manufacturing precision through a systematic multi-step process.
2Reliability
If uniform semiconductor layer thickness is used, then manufacturing is easier, but performance optimization is limited due to current variations
Solution Approach 1:
The patent implements local quality by designing the semiconductor layer with spatially varying thickness characteristics. The semiconductor layer comprises a first region with a first thickness and a second region with a second thickness different from the first thickness. This non-uniform structure allows different regions to be optimized for their specific functions: regions with greater thickness can provide higher current conduction for ON state, while regions with reduced thickness can minimize leakage for OFF state, thereby optimizing overall memory die performance.
Solution Approach 2:
The patent applies segmentation by dividing the semiconductor layer into multiple distinct regions with different thickness characteristics. The semiconductor layer is segmented into a first region and a second region (and potentially additional regions), each with controlled thickness variations. This segmentation enables independent optimization of each region's electrical characteristics, allowing the overall device to achieve superior performance by combining regions optimized for different functions (high current conduction vs. low leakage).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ON current while minimizing OFF current and leakage, improving the yield and performance of memory dies by controlling semiconductor layer thickness and structure through precise manufacturing steps.
Implementation Method 1
performing oxidation treatment on the semiconductor layer to form an oxide film
Data Source
AI summary
A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a first insulating portion and the first conductive layer, a second region between a second insulating portion and the second conductive layer, and a third region between the first region and the second region. The third region includes a fourth region extending in a second direction, a fifth region between the first region and the fourth region, a sixth region between the second region and the fourth region, and a seventh region between the fifth region and the first region and extending in the first direction.