Storage Node Contact Layout for Uniform Memory Cell Etching
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Solution Overview
Problem
Existing semiconductor memory devices with recessed gate structures face defects and low yield due to limitations in fabrication technology, affecting the efficiency and reliability of memory devices.
Innovation Solution
The formation of storage node contacts and dummy storage node contacts within dense and iso regions of the semiconductor memory device, using a substrate with buried word lines and shallow trench isolation, allows for improved fabrication yield and reliability by maintaining consistent luminous flux during photolithography, and eliminates additional fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography is performed on regions with varying component densities, then manufacturing complexity increases, but manufacturing precision deteriorates due to micro loading effects
Solution Approach 1:
The patent applies local quality by introducing dummy storage node contacts specifically in iso regions where component density is lower, while maintaining regular storage node contacts in dense regions. This local differentiation compensates for micro loading effects in specific areas without altering the overall device design, thereby achieving uniform etching across regions with varying component densities.
Solution Approach 2:
The dummy storage node contacts are formed in advance during the same fabrication process as the regular storage node contacts, before final device operation. This preliminary action ensures that etching uniformity is established during manufacturing without requiring additional process steps or post-processing adjustments.
2Manufacturing precision
If additional fabrication processes are performed to address micro loading effects, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
The patent merges the formation of dummy storage node contacts with the existing storage node contact fabrication process. Both regular and dummy contacts are formed in the same etching and filling steps, eliminating the need for separate process sequences. This integration maintains etching uniformity while avoiding productivity loss from additional fabrication steps.
Solution Approach 2:
The dummy storage node contacts serve multiple functions: they compensate for micro loading effects in iso regions, maintain etching uniformity across the substrate, and are formed using the same process steps as regular storage node contacts. This multi-functionality achieves manufacturing precision improvement without sacrificing productivity.
3Reliability
If recessed gate structures are used to reduce leakage current, then reliability improves, but manufacturing precision deteriorates due to incomplete etching in dense regions
Solution Approach 1:
The patent applies local quality by differentiating between dense regions (with regular storage node contacts supporting recessed gate structures) and iso regions (with dummy storage node contacts). This local differentiation ensures that recessed gate structures achieve their leakage reduction benefit in dense regions while dummy contacts in iso regions prevent etching inconsistencies from propagating across the substrate.
Solution Approach 2:
The dummy storage node contacts are formed in advance to establish uniform etching conditions before the recessed gate structure fabrication. This preliminary action prevents incomplete etching issues from affecting the reliability-critical recessed gate structures in subsequent processing steps.
Data Source
AI summary
The present disclosure provides a semiconductor memory device and a fabricating method thereof, which includes a substrate, a plurality of buried word lines, and a plurality of storage node contacts. The substrate includes a plurality of active areas and a shallow trench isolation. The buried word lines are embedded in the substrate, across the shallow trench isolation and the active areas. The storage node contacts directly contact the active areas and include a plurality of first plugs, with each first plug including an insulating material and a conductive material stacked sequentially from bottom to top. Within the semiconductor memory device, at least one active area simultaneously contacts two of the first plugs, or a storage node pad physically contacts at least two of the first plugs. Thus, the present disclosure is beneficial on forming the semiconductor memory device with better component reliability.