Storage Node Contact Overlay in Buried Gate DRAM
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is the high contact resistance due to the small contact area between storage node contacts and active regions in buried gate structures, which limits the scalability and efficiency of DRAM memory cells.
Innovation Solution
The solution involves forming an isolation pattern on a device isolation structure with contact plugs at its sides to ensure full overlap with the active region, increasing the etching width of storage node contacts, and using materials like nitride and amorphous carbon layers with different etch selectivity to prevent pattern collapse and improve processing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory cell size is reduced to fit more cells in the same area, then storage capacity increases, but the contact area between storage node contact and active region decreases leading to higher contact resistance
Solution Approach 1:
The patent introduces a vertical dimension by forming the isolation pattern on top of the device isolation structure. This additional vertical layering allows horizontal contact area to be increased without expanding the planar footprint of the memory cell, thus maintaining high storage capacity while improving contact characteristics.
2Device complexity
If conventional etching processes are used without isolation patterns, then the manufacturing process is simpler, but overlay alignment is difficult and processing margin is reduced
Solution Approach 1:
The isolation pattern serves as an intermediary structure that facilitates precise alignment during etching processes. It acts as a reference feature that enables better overlay control without significantly complicating the overall manufacturing process flow.
Solution Approach 2:
The isolation pattern is formed in advance before the critical contact etching steps. This preliminary action establishes precise alignment references that guide subsequent etching processes, improving overlay accuracy and processing margin before the actual contact formation occurs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance, enhances processing margins, and allows for more efficient packing of memory cells by ensuring full overlap and increased contact area between storage node contacts and active regions, thereby improving the scalability and performance of DRAM memory cells.
Implementation Method 1
The isolation pattern may include an insulating layer having a different etch selectivity from an oxide layer
Data Source
AI summary
A semiconductor device and a method of fabricating the same are provided, in which a full overlap between a storage node contact and an active region to solve an overlay in an etching process and an etching width of a storage node is increased to improve a processing margin. The semiconductor device includes a main gate and a device isolation structure disposed in a semiconductor device, an isolation pattern disposed over the device isolation structure, and contact plugs disposed at each side of the isolation pattern.