Narrower Storage Node Contact Plugs for Semiconductor Memory

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Solution Overview

Problem

Current semiconductor memory devices face challenges in achieving high reliability due to limitations in integration density and fabrication process margins, particularly in ensuring effective electrical characteristics and preventing electrical short circuits and excessive etching during the formation of storage plugs.

Innovation Solution

The semiconductor memory device design includes a buried gate structure with a conductive landing pad and storage node contact plug configuration, where the landing pad has a wider width than the doped region, and the storage node contact plug is narrower, along with an interconnection plug and line with similar widths, to enhance electrical isolation and prevent direct contact with the active region, thereby reducing the risk of electrical shorts and excessive etching.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of moving object

If the storage node contact plug is made narrower to increase integration density, then the contact area with the doped region is reduced, but this increases the risk of electrical shorts and excessive etching

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical characteristics reliability
Core Design Contradiction:
Area of moving objectVSReliability

Solution Approach 1:

The patent introduces a landing pad as an intermediary structure between the storage node contact plug and the doped region. The landing pad has a width greater than both the contact plug and the doped region, creating overlapping areas that ensure adequate contact area even when the contact plug is narrow. This mediator structure prevents direct contact between the narrow plug and the doped region, eliminating the risk of electrical shorts and excessive etching while maintaining high integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the landing pad width is increased to prevent electrical shorts, then the overlap area with the doped region is improved, but the device complexity increases

Engineering Contradiction:
Improveelectrical isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the landing pad formation process with the existing interconnection structure formation. The landing pad is formed as part of the conductive interconnection layer that also creates the interconnection plug and line, utilizing the same deposition and patterning steps. This integration approach increases reliability through improved electrical isolation without proportionally increasing device complexity, as the additional structure is created within the existing process framework.

Inventive Principle:
Principle #5Merging (Combining)

3Ease of manufacture

If the interconnection plug and line have similar widths to maintain alignment, then the fabrication process is simplified, but the electrical isolation from the active region is reduced

Engineering Contradiction:
Improvealignment precisionVSAvoidelectrical isolation
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent resolves the conflict between alignment simplicity and electrical isolation by introducing a width variation in the vertical dimension of the structure. The landing pad is formed with a width greater than both the interconnection plug and the doped region, creating overlapping areas in the planar dimension. This dimensional approach allows the interconnection plug and line to maintain similar widths for easy alignment while the wider landing pad provides enhanced electrical isolation and contact area in a different spatial dimension.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8878273B2Semiconductor memory device including narrower storage node contact plugs
Publication Date: 2014.11.04 SAMSUNG ELECTRONICS CO LTD
  • US8878273B2 patent drawing
  • US8878273B2 patent drawing
  • US8878273B2 patent drawing

AI summary

A semiconductor memory device includes an active region protruding from a substrate. The active region includes first and second doped regions therein and a trench therein separating the first and second doped regions. A buried gate structure extends in a first direction along the trench between first and second opposing sidewalls thereof. A conductive interconnection plug is provided on the first doped region adjacent the first sidewall of the trench, and a conductive landing pad is provided on the second doped region adjacent the second sidewall of the trench. The landing pad has a width greater than that of the second doped region of the active region along the first direction. A conductive storage node contact plug is provided on the landing pad opposite the second doped region. The storage node contact plug has a narrower width than the landing pad along the first direction.