Storage Node Contact Formation Between Bit Lines Without Void Filling
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Solution Overview
Problem
In semiconductor devices, the high width-to-depth ratio of positions filled with polysilicon for Storage Node Contact (SNC) structures between Bit Lines (BLs) and active areas leads to voids at the bottoms of the SNC structures, affecting yield.
Innovation Solution
A method for forming a semiconductor structure involves forming a substrate with active areas and isolation structures, etching a conductive layer to create bit line grooves and conductive lines, forming bit line structures within these grooves, and etching conductive lines to form conductive pillars serving as storage node contact structures, thereby reducing the need for filling contact holes and simplifying the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If polysilicon is used to prepare Storage Node Contact structures between Bit Lines and active areas, then the SNC structures can be formed, but voids appear at bottoms of the formed SNC structures due to high width-to-depth ratio, affecting yield
Solution Approach 1:
Instead of filling contact holes from top to bottom (conventional approach), the patent forms bit line grooves first, then forms bit line structures within them, and finally forms storage node contact structures by etching conductive lines. This inverted sequence eliminates the need to fill high aspect ratio contact holes, thereby preventing void formation and improving filling quality.
Solution Approach 2:
The patent segments the formation process into distinct stages: forming bit line grooves, forming bit line structures, and forming storage node contact structures. This segmentation allows each structure to be formed independently with optimized process parameters, avoiding the need to fill difficult-to-access contact holes and eliminating void formation.
2Ease of manufacture
If conventional filling methods are used to form Storage Node Contact structures, then contact structures can be formed, but the process becomes complex and time-consuming
Solution Approach 1:
The patent merges the formation of bit line structures and storage node contact structures into a unified process flow. Bit line grooves are formed first, then bit line structures are formed within them, and storage node contact structures are formed by etching conductive lines. This merging eliminates separate filling steps and reduces manufacturing cycle time.
Solution Approach 2:
The patent performs preliminary actions by forming bit line grooves and bit line structures before forming storage node contact structures. This preliminary preparation simplifies subsequent steps and eliminates the need for complex filling operations, thereby reducing manufacturing cycle time and improving ease of manufacture.
3Device complexity
If Bit Line Contact structures and contact hole filling are used, then electrical connection is achieved, but device complexity increases
Solution Approach 1:
The patent extracts the bit line contact function from separate Bit Line Contact structures and integrates it directly into the bit line groove structure. The bit line structure itself serves as the electrical connection element, eliminating the need for separate BLC structures and reducing overall device complexity while maintaining reliable electrical connection.
Solution Approach 2:
The bit line groove structure serves multiple functions: it provides the bit line structure itself, provides the electrical connection pathway, and defines the storage node contact formation area. This multi-functionality reduces the number of separate structures needed, thereby reducing device complexity while ensuring reliable electrical connection.
Data Source
AI summary
A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.