Storage System Node Modules Mesh Network Scalability

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Solution Overview

Problem

Current storage systems face challenges in efficiently distributing data across multiple nodes in a network, leading to reduced throughput due to concentrated access and limited scalability, especially in cloud computing environments where multiple information processors are connected.

Innovation Solution

A storage system configuration featuring a mesh network of node modules (NMs) connected through interfaces, allowing efficient data transmission and distribution across multiple paths, with a management module (MM) for monitoring and controlling the network, and an interface unit (I/F unit) for expanding and connecting multiple storage systems as one unified memory unit.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple information processors are connected through a network to operate as one system, then system scalability is improved, but throughput reduction due to concentrated access increases

Engineering Contradiction:
Improvesystem scalabilityVSAvoidthroughput
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The storage system is divided into multiple independent node modules (NMs), each capable of autonomous data storage and processing. This segmentation allows data to be distributed across multiple nodes, preventing concentrated access bottlenecks while maintaining system scalability through modular expansion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a mesh network topology that adds spatial dimensionality to data access paths. Instead of linear or hierarchical access structures, multiple dimensional pathways enable parallel data retrieval across the network, improving throughput while supporting system expansion.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If data is distributed across multiple nodes, then system reliability is improved, but data distribution efficiency decreases

Engineering Contradiction:
Improvesystem reliabilityVSAvoiddata distribution efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The management module implements feedback mechanisms that monitor network conditions, node status, and data access patterns. This feedback enables dynamic optimization of data distribution routes and node workload allocation, maintaining high distribution efficiency while ensuring data is reliably distributed across multiple nodes for enhanced system reliability.

Inventive Principle:
Principle #23Feedback

3Quantity of substance

If multiple DRAM chips or NAND flash chips are connected through wiring, then storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple DRAM chips or NAND flash chips are merged into unified node modules with integrated control logic. This merging approach increases storage capacity while managing complexity by consolidating chip interconnections through standardized wiring patterns and modular architecture, preventing exponential complexity growth.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9891841B2Storage system including a plurality of memory nodes connected through first and second groups of interfaces
Publication Date: 2018.02.13 KIOXIA CORP
  • US9891841B2 patent drawing
  • US9891841B2 patent drawing
  • US9891841B2 patent drawing

AI summary

A storage system includes a memory unit group that includes a first memory unit and a plurality of second memory units, and the first memory unit is connected to the plurality of second memory units so that data can be transmitted between the first memory unit and the second memory units. The plurality of second memory units is mounted on a same first substrate. One second memory unit of the plurality of second memory units cooperates with the first memory unit and does not cooperate with the other second memory units of the plurality of second memory units.