Storage Device Over-Program Management via Voltage Adjustment

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Solution Overview

Problem

Current storage devices face challenges in maintaining data integrity and reliability due to over-programming issues, where memory cells are programmed beyond their intended threshold voltage, leading to data loss and reduced device performance.

Innovation Solution

A storage device and operating method that include a memory cell array, a program operation controller, a voltage generator, and an over-program manager. The over-program manager adjusts operating voltages based on the number of over-programmed memory cells, increasing voltages for subsequent states and designating over-programmed cells as 'bad blocks' to prevent further data loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are programmed to higher threshold voltage states to increase storage capacity, then the storage density is improved, but the risk of over-programming increases leading to data integrity degradation

Engineering Contradiction:
Improvestorage capacityVSAvoiddata integrity
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the verify operation controller continuously monitors the threshold voltage of memory cells during programming. When over-programming is detected (threshold voltage exceeds the range for the target state), the system provides feedback to adjust subsequent programming operations, thereby preventing data integrity degradation while maintaining high storage capacity

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary verification operations before completing the programming process to higher threshold voltage states. By checking the threshold voltage at intermediate stages and adjusting programming parameters in advance, the system prevents over-programming from occurring, thus maintaining data integrity while enabling high-density storage

Inventive Principle:
Principle #10Preliminary action

2Reliability

If verify operations are performed more frequently to detect over-programmed cells, then data integrity is improved, but the programming time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprogramming time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial verification by performing verify operations on selected memory cells rather than all cells, and uses adaptive verification where the frequency and depth of verification is adjusted based on the programming state. This selective approach maintains data integrity through sufficient verification while minimizing the time penalty

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent implements dynamic verification where the verify operation controller adapts the verification strategy based on real-time conditions. When over-programming risk is high, verification is intensified; when programming proceeds normally, verification is reduced. This dynamic adjustment maintains data integrity while optimizing programming time

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10643724B2Storage device and operating method thereof
Publication Date: 2020.05.05 MIMIRIP LLC
  • US10643724B2 patent drawing
  • US10643724B2 patent drawing
  • US10643724B2 patent drawing

AI summary

In a memory device having improved reliability, the memory device includes: a memory cell array including memory cells; a program operation controller configured to perform a program operation on the memory cells to any one state among first to nth states; a voltage generator configured to generate operating voltages respectively corresponding to the first to nth states in the program operation; a verify operation controller configured to verify whether the program operation performed on selected memory cells to a kth state, has been completed, and count a number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the kth state among the selected memory cells; and an over-program manager configured to increase operating voltages corresponding to (k+1)th to nth states to be greater than default values according to the number of over-programmed memory cells.