Multi-Core Storage Power Management via Command Pattern Analysis
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Solution Overview
Problem
Multi-core processors in storage devices increase power consumption, shortening battery life in devices like notebook computers, necessitating a method to efficiently manage electric power.
Innovation Solution
A method that analyzes command patterns to select operation modes, using a single processing core for power management in performance mode and separate cores for each function block in low power mode, and changing states to minimize power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a multi-core processor is used in a storage device, then the storage device operates more quickly, but the power consumption increases
Solution Approach 1:
The patent implements dynamic power management by switching between different power modes (first power mode and second power mode) based on operational conditions. The system transitions from a static power consumption model to a dynamic one where power usage adapts to workload requirements, allowing the storage device to maintain high speed when needed while reducing power consumption during lower-demand periods.
Solution Approach 2:
The patent divides the processing functionality into separate processing cores, each responsible for specific functions. This segmentation allows individual cores to be activated or deactivated based on current operational needs, enabling the system to maintain high processing speed when multiple cores are active while reducing overall power consumption when fewer cores are required.
2Productivity
If a multi-core processor is used in a storage device, then the processing capability increases, but the battery life is shortened
Solution Approach 1:
The system dynamically adjusts its power consumption profile by switching between operational modes. In the first power mode, the system maintains high processing capability with all processing cores active. In the second power mode, the system reduces power consumption by deactivating certain cores, thereby extending battery life while maintaining sufficient processing capability for typical operations.
Solution Approach 2:
The patent changes operational parameters such as the number of active processing cores, clock frequencies, and power states based on detected conditions. By adjusting these parameters dynamically, the system can extend battery life by reducing the aggregate power consumption of multiple cores while preserving the ability to deliver high processing capability when necessary.
3Productivity
If separate processing cores manage different function blocks, then power management efficiency improves, but system complexity increases
Solution Approach 1:
The patent segments the power management function across separate processing cores, with each core responsible for managing specific function blocks. This segmentation improves power management efficiency by enabling parallel power management operations and reducing the workload on any single core, while the modular architecture helps manage system complexity through clear functional division.
Solution Approach 2:
The patent implements a universal power management approach where processing cores can operate in different modes (first power mode with centralized management, second power mode with distributed management) depending on system conditions. This multi-functionality allows the same hardware architecture to adapt to different operational requirements, improving power management efficiency without permanently increasing system complexity.
Data Source
AI summary
A method of managing power of the storage device including a first processing core for controlling a first function block and a second processing core for controlling a second function block includes: analyzing a pattern of commands received from the outside; selecting an operation mode of the storage device based on the analyzed pattern; and managing the electric power of the storage device by using the first processing core if the selected operation mode is a first mode, and separately managing electric powers of the first and second function blocks by using the first and second processing cores, respectively, if the selected operation mode is a second mode.