Storage Processing Units Interconnect Network Host Interface Offloading
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Solution Overview
Problem
In traditional SSD storage arrays, the host interface becomes a bottleneck due to high communication demands between storage processing units, leading to saturation and inefficient processing tasks.
Innovation Solution
Implementing an interconnection network that allows direct data transfers between storage processing units, offloading processing tasks from the host to these units, thereby reducing the workload on the host interface and enhancing communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If host interface bus (PCIe) is used for communication between storage processing units, then compatibility with existing host systems is maintained, but communication speed becomes a bottleneck and host interface becomes saturated
Solution Approach 1:
The system segments the communication path by introducing an interconnect network layer between storage processing units and the host interface. This separates the high-speed internal storage communication from the host interface bus, allowing parallel data transfer paths that prevent host interface saturation while maintaining compatibility with existing host systems through the standard host interface.
Solution Approach 2:
An interconnect network is introduced as an intermediary component between storage processing units and the host. This intermediary enables direct peer-to-peer communication between storage units through the interconnect network, bypassing the host interface bus for internal data transfers, thereby eliminating the bottleneck while preserving host interface compatibility for host-initiated operations.
2Productivity
If storage arrays handle all storage tasks independently, then processing efficiency is improved, but communication between storage processing units becomes saturated on host interface bus
Solution Approach 1:
The communication traffic is segmented into two distinct paths: host-initiated commands through the host interface bus and storage unit-to-storage unit data transfers through the interconnect network. This segmentation allows high-volume inter-storage communication to occur independently of host interface capacity constraints, enabling parallel processing without interface saturation.
Solution Approach 2:
The interconnect network serves as an intermediary communication channel that handles the bulk of storage unit-to-storage unit traffic. By routing internal storage communications through this dedicated intermediary network rather than through the host interface bus, the system accommodates high communication traffic volumes without saturating the host interface.
3Device complexity
If peer-to-peer communication through host interface is used, then system simplicity is maintained, but communication throughput is limited by host bus speed
Solution Approach 1:
The communication function is segmented into two independent pathways: simple host-to-storage commands through the existing host interface and high-throughput peer-to-peer data transfers through the new interconnect network. This segmentation allows the system to maintain simplicity for basic operations while achieving high throughput for data-intensive tasks through the specialized interconnect path.
Solution Approach 2:
The storage array system is designed with multi-functionality to handle different communication needs through appropriate pathways. The host interface handles host control and simple commands, while the interconnect network handles high-speed peer-to-peer data transfers. This universal design allows the system to maintain simplicity for basic operations while providing high throughput capability when needed.
Data Source
AI summary
Systems and methods for offloading processing from a host to one or more storage processing units using an interconnect network are provided. One such method includes receiving a processing task from the host at a first storage processing unit (SPU) of a plurality of SPUs via a host interface, performing, at the first SPU, the processing task, and transferring data from the first SPU to a second SPU via an interconnection network, where each of the plurality of SPUs includes a non-volatile memory (NVM) and a processing circuitry configured to perform the processing task.