Storage Processor I/O Priority Queuing for Nonvolatile Memory
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Solution Overview
Problem
Existing command queuing systems, particularly those optimized for electromechanical hard drives, are ineffective for semiconductor-based nonvolatile storage as they do not account for the physical placement of data, leading to increased latency and inefficiencies in data access.
Innovation Solution
A memory system with priority-based Input/Output (I/O) command queuing for nonvolatile semiconductor memory, utilizing a storage processor with a command interface, expectation table, and mode selector to manage external and internal priorities, and switch between standard and preemption operational modes based on queue depth and request latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If command queuing is implemented to minimize rotational and seek delay for hard drives, then access latency is reduced, but the system provides no benefit for semiconductor-based nonvolatile storage and may increase overall system latency
Solution Approach 1:
The command queuing system dynamically adapts its behavior based on the type of storage device being accessed. For hard drives, it implements rotation and seek optimization, while for semiconductor-based storage, it uses a different queuing strategy that does not introduce unnecessary latency. This dynamic adaptation resolves the contradiction by making the system versatile across different storage types while maintaining optimal performance for each.
Solution Approach 2:
The system changes the queuing parameters and command scheduling behavior based on the storage device type. When detecting semiconductor-based nonvolatile storage, it modifies the command queuing parameters to avoid the mechanical optimization routines that would increase latency, thereby maintaining adaptability while reducing access latency for the specific storage type.
2Speed
If priority-based command scheduling is implemented, then critical I/O operations are serviced faster, but overall system latency increases due to reordering commands
Solution Approach 1:
The system implements partial preemption where only high-priority commands that exceed their expected completion time are interrupted and serviced immediately. Not all commands are subjected to preemption, which avoids the overhead of constant priority checking and reordering. This selective approach speeds up critical operations while minimizing the impact on overall system latency.
Solution Approach 2:
The system uses an expectation table that tracks the expected completion time for each priority level. When a command's actual completion time exceeds its expected time, the system provides feedback and triggers preemption. This feedback mechanism ensures that priority-based scheduling only intervenes when necessary, reducing overall latency while still meeting critical timing requirements.
3Ease of operation
If multiple priority levels are supported with separate queues, then I/O priority management is enhanced, but device complexity increases
Solution Approach 1:
The command queue is segmented into multiple priority-level queues, with each queue handling commands of a specific priority. This segmentation allows for simple, independent management of each priority level without requiring complex inter-queue coordination. The segmented structure enhances ease of priority management while keeping the complexity of individual queue management relatively low.
Solution Approach 2:
The expectation table serves multiple functions: it stores expected completion times for different priority levels, tracks actual completion times, determines when preemption should occur, and provides feedback for dynamic priority adjustment. This multi-functionality reduces the need for separate complex structures for each function, thereby managing device complexity while providing comprehensive priority management.
Data Source
AI summary
In one embodiment, a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory comprises one or more banks of electrically erasable semiconductor memory coupled to a storage processor. The storage processor can processes access requests for the memory, and has components including: a command interface, an expectation table, and a mode selector. The command interface receives memory access requests, which include a tag to identify the request, and an external priority associated with the request. The expectation table includes a set of times associated with each of the external priority levels, which indicate the period in which a request having the external priority is expected. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode.