Storage Processor Multi-Stage Request Processing

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Solution Overview

Problem

Conventional storage systems face significant slowdowns when processing requests with large working sets and poor spatial locality, leading to frequent thrashing between processor cache and memory, which reduces the speed of request servicing.

Innovation Solution

The improved technique processes workflow in stages, where each request is assigned to a core and placed in a first queue, with a single thread executing initial instructions for a prespecified number of requests before moving to second instructions, minimizing thrashing by optimizing cache usage and reducing excessive switching between cache and memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If a single thread processes each request from start to completion, then request processing is simple to implement, but processing speed significantly slows down for requests with large working sets and poor spatial locality

Engineering Contradiction:
Improvesimplicity of implementationVSAvoidrequest processing speed
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments the request processing workflow into multiple stages (e.g., cache lookup stage, address translation stage, data retrieval stage) and introduces intermediate queues between stages. Each stage processes a batch of requests independently before passing them to the next stage, transforming a single-threaded sequential process into a multi-stage pipeline that improves throughput while maintaining implementation simplicity.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the working set size exceeds processor cache capacity, then all requests can be accommodated in memory, but frequent thrashing between cache and memory occurs

Engineering Contradiction:
Improveworking set sizeVSAvoidprocessing speed
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides the large working set into smaller subsets that fit within processor cache capacity by processing requests in batches through multiple stages. Each stage maintains its own working set in cache, avoiding the need to hold the entire request sequence in memory while preventing frequent cache-memory thrashing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary processing of requests in early stages (such as cache lookup and address translation) before passing them to subsequent stages. This preliminary action prepares data in advance in a format optimized for cache utilization, reducing the need for repeated cache-memory accesses during later processing stages.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If instructions for each task are executed sequentially in a single thread, then implementation is straightforward, but spatial locality is poor causing excessive cache switching

Engineering Contradiction:
Improveimplementation straightforwardnessVSAvoidcache switching time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The patent segments the instruction execution flow into stage-specific instruction sets that are executed in batches. Each stage has its own optimized instruction sequence that processes multiple requests using similar operations, improving spatial locality by keeping related instructions in cache together and reducing cache switching overhead.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10235203B1Techniques for increasing storage system performance in processor-bound workloads with large working sets and poor spatial locality
Publication Date: 2019.03.19 EMC IP HLDG CO LLC
  • US10235203B1 patent drawing
  • US10235203B1 patent drawing
  • US10235203B1 patent drawing

AI summary

An improved technique involves processing a workflow in stages, and processing all requests in a queue for a given stage before moving onto the next stage. Along these lines, each request received by a storage processor is assigned to a core and placed in a first queue for that core. Within that core, a single system thread executes first instructions for a task, e.g., checking the storage cache for the requested data from a request, and then transfers the request to a second queue. Rather than perform additional tasks to completely satisfy the request, however, the thread executes the first instructions for a prespecified number of requests in the first queue. Only when the thread has executed instructions for the prespecified number of requests, the thread begins execution of second instructions for requests in the second queue, and work on the next task begins.