Storage Device Read-Ahead Caching to Reduce Read Latency

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Solution Overview

Problem

Storage devices experience increased latency due to repeated read operations from the same address, necessitating improved methods to reduce read latency.

Innovation Solution

A storage device with a non-volatile memory, buffer memory, and storage controller that selectively stores frequently accessed data in a buffer memory for rapid retrieval, adjusting buffer regions based on read frequency and address ranges, and utilizing a faster buffer memory for direct data output when the address matches the stored range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If data is repeatedly read from the same address in non-volatile memory, then data access is performed, but read latency increases

Engineering Contradiction:
Improveread latencyVSAvoiddata read performance
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The storage controller pre-loads data from non-volatile memory into the buffer memory before actual read requests occur. When dataset management commands are received, the controller identifies logical block address ranges and proactively transfers corresponding data to the buffer, so that subsequent read operations can be served from the buffer without accessing the slower non-volatile memory again.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buffer memory acts as an intermediary between the host device and the non-volatile memory. It caches frequently accessed data, allowing the system to serve read requests from this intermediate storage layer, thereby reducing the need for direct access to the slower non-volatile memory and lowering read latency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Speed

If buffer memory is used to cache data, then read speed increases, but device complexity increases

Engineering Contradiction:
Improvedata read speedVSAvoidstorage device structure
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The buffer memory serves multiple functions: it acts as a cache for frequently accessed data, stores metadata about dataset management commands, and provides temporary storage during data transfer operations. This multi-functionality justifies the added complexity by providing comprehensive performance benefits across different operational scenarios.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system dynamically manages the buffer memory based on actual read patterns and dataset management commands. The controller adapts by receiving dataset management commands, identifying relevant logical block address ranges, and selectively loading data into the buffer, making the buffer utilization flexible and responsive to actual system needs rather than statically configured.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12417175B2Storage device and data processing method
Publication Date: 2025.09.16 SAMSUNG ELECTRONICS CO LTD
  • US12417175B2 patent drawing
  • US12417175B2 patent drawing
  • US12417175B2 patent drawing

AI summary

A storage device includes a non-volatile memory, a buffer memory, and a storage controller. The controller receives first host data indicating a first logical block address range of the non-volatile memory from a host device, reads first memory data from the non-volatile memory using the first logical block address range, and stores the first memory data in the buffer memory. The storage controller further receives a read command and a read address from the host device, determines whether the read address is within the first logical block address range, read, in response to the read address being determined as within the first logical block address range and the read command, the first memory data from the buffer memory, without accessing the non-volatile memory, and outputs the first memory data from the buffer memory to the host device.