Storage Device Read Cache Memory Hot Data Interleaving

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Solution Overview

Problem

Storage devices face performance degradation due to data with high read frequencies being stored in a single memory device, which prevents data interleaving and reduces read efficiency.

Innovation Solution

Incorporating a read cache memory block and a memory controller that identifies data with read counts exceeding a threshold value, spreading this data across multiple memory devices for interleaved reading, enhancing read performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If data with high read frequency is stored in a single memory device, then data access simplicity is improved, but read performance deteriorates due to prevention of data interleaving

Engineering Contradiction:
Improvedata access simplicityVSAvoidread performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent segments frequently accessed data (hot data) from regular data by identifying it through read count thresholds and storing it in separate read cache memory blocks within memory devices. This segmentation enables independent access paths: hot data can be read from cache blocks while other data operations proceed normally, thus maintaining operational simplicity while enabling parallel read operations through data interleaving across multiple devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension to data storage by adding read cache memory blocks as a separate storage layer within each memory device. This dimensional addition creates a hierarchical structure where hot data resides in cache blocks and other data resides in main memory blocks, enabling simultaneous access to different data types without conflict and improving overall read throughput through interleaved operations.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If data is spread across multiple memory devices for interleaved reading, then read performance is improved, but device complexity increases

Engineering Contradiction:
Improveread performanceVSAvoidmemory system complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the read cache functionality directly into each memory device by incorporating read cache memory blocks within the memory device structure itself. This merging eliminates the need for separate external cache systems and integrates cache management into the existing memory controller, thereby achieving performance improvement through data spreading while minimizing additional system complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Each memory device equipped with read cache memory blocks autonomously manages its own hot data storage and retrieval operations. The memory controller identifies hot data and directs it to appropriate cache blocks within respective memory devices, enabling self-service cache management without requiring complex centralized control mechanisms, thus improving performance while keeping complexity manageable.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10853236B2Storage device and method for operating the same
Publication Date: 2020.12.01 SK HYNIX INC
  • US10853236B2 patent drawing
  • US10853236B2 patent drawing
  • US10853236B2 patent drawing

AI summary

A storage device and a method of operating the storage device include various memory devices. The storage device includes a plurality of memory devices each including at least one or more read cache memory blocks and a plurality of main memory blocks; and a memory controller configured to spread and store data stored in an identical memory device, having a read count representing a number of read requests and exceeding a threshold value, among data stored in the plurality of main memory blocks, to the at least one or more read cache memory blocks included in each of the plurality of memory devices.