Non-volatile Storage Device Read Cache Interrupt Timing
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Solution Overview
Problem
High-speed memory interfaces face challenges when accessing low-speed flash memory devices, leading to potential data corruption due to timely data return issues, and existing solutions are not effective in managing varying operation states of flash memory chips during read and write operations.
Innovation Solution
A non-volatile storage device with an interface module, control module, and read/write cache that sends interrupt signals to the host to manage data retrieval and storage efficiently, ensuring correct data handling and optimizing operations based on the flash memory's state, thereby preventing incorrect data usage during read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high-speed memory interface is used to access flash memory, then the bandwidth and access speed are improved, but the host may obtain incorrect data when the flash memory cannot return data in time
Solution Approach 1:
The patent uses a read cache to pre-store data from the flash memory chip before the host needs it. When the host initiates a read operation, the data is already prepared in the read cache, eliminating the timing mismatch between the high-speed interface and slow flash memory. This preliminary action ensures data correctness while maintaining high interface speeds.
Solution Approach 2:
The read cache acts as an intermediary buffer between the high-speed memory interface and the low-speed flash memory chip. It absorbs the speed difference by pre-loading data, allowing the host to read from the fast cache while the flash memory operates at its slower pace, thus preventing data corruption.
2Reliability
If the host waits for flash memory to return data within the read operation period, then data correctness is maintained, but the read efficiency and throughput are reduced
Solution Approach 1:
The read cache pre-stores data from the flash memory chip before the host needs it. This preliminary action allows the host to read data immediately without waiting for the slow flash memory, thus maintaining both data correctness and high read efficiency.
Solution Approach 2:
While the host is reading data from the read cache, the control module continues to read new data from the flash memory chip and store it in the read cache. This continuous preparation of data ensures that the host never waits, maintaining continuous useful action and high productivity.
3Device complexity
If the flash memory chip is used directly without cache, then the device complexity is reduced, but the host cannot obtain correct data due to timing mismatches
Solution Approach 1:
The read cache serves as a simple intermediary component between the host and flash memory chip. It resolves the timing mismatch problem with minimal added complexity, ensuring data correctness while maintaining a relatively simple overall device structure.
4Productivity
If the host initiates multiple read operations quickly, then the throughput is improved, but the flash memory chip cannot complete operations in time leading to data errors
Solution Approach 1:
The read cache pre-loads data from the flash memory chip in advance, so when the host initiates multiple rapid read operations, the data is already prepared and available. This preliminary action allows high throughput without compromising data correctness, as the host reads from the fast cache rather than waiting for slow flash memory operations.
Solution Approach 2:
The control module continuously reads data from the flash memory chip and stores it in the read cache in the background, independent of host read operations. This continuous data preparation ensures that multiple rapid host read requests can be satisfied immediately, maintaining both high throughput and data correctness.
Data Source
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AI summary
A non-volatile storage device is disclosed. The non-volatile storage device includes an interface module (11), a control module (12), a read cache (13), and a storage chip (14). The interface module is configured to: receive a first read request signal sent by a host (401), where the first read request signal includes an address of the storage chip; when read data requested by the first read request signal is not stored in the read cache (402), instruct the control module to read the read data from the storage chip (403); and before the host ends a current read operation period, send a first interrupt signal (404) and predetermined data (405) to the host, where the predetermined data is used to cause the host to end the read operation period, and the first interrupt signal is used to instruct the host to execute an interrupt handler after the read operation period (406). In this way, the interrupt signal is sent, so that the host enters the interrupt handler to wait for correct data, preventing the host from obtaining incorrect data to perform a subsequent operation.