Storage Device Reset Control Circuit for Power Loss Protection
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Solution Overview
Problem
Semiconductor storage devices, such as SSDs, face issues with abnormal reset operations due to sudden power loss, leading to potential errors and reduced reliability, as existing methods fail to ensure complete reset operations.
Innovation Solution
A method involving a storage device with a power-loss protection integrated circuit (PLP IC) that generates an internal power supply voltage, a reset detector for generating first and second reset control signals, and a reset controller to create a final reset control signal, ensuring a controlled reset operation even after external power supply voltage is turned off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a simple reset operation is used, then the device complexity is reduced, but the reliability deteriorates due to abnormal reset offs during power loss
Solution Approach 1:
The reset control function is segmented into multiple independent components: a reset detector that monitors power conditions, a reset controller that processes reset signals, and a storage controller that executes the actual reset operation. This segmentation allows each component to perform its specific function reliably, preventing abnormal reset offs while maintaining manageable complexity through modular design
Solution Approach 2:
The reset detector continuously monitors the power supply voltage and provides feedback to the reset controller. When power loss is detected, the feedback mechanism triggers the storage controller to execute a controlled reset operation, ensuring reliable reset behavior under varying power conditions without requiring complex manual intervention
2Reliability
If the reset operation is not completed normally, then the device can avoid complex reset procedures, but operation errors occur in the storage controller
Solution Approach 1:
The reset detector performs preliminary monitoring of power supply conditions before the actual reset operation begins. By detecting power loss in advance and triggering the reset sequence beforehand, the system ensures that the storage controller receives proper reset signals at the appropriate timing, preventing operation errors while maintaining efficient reset execution
Solution Approach 2:
The reset controller acts as an intermediary between the reset detector and the storage controller. It receives power condition information from the detector and translates it into appropriate reset signals for the storage controller, ensuring reliable and error-free reset operations without requiring direct complex interactions between the other components
3Reliability
If the storage device uses external power supply only, then the device complexity is reduced, but the reliability deteriorates during sudden power loss
Solution Approach 1:
The system prepares for power loss scenarios by implementing a power-loss protection mechanism that activates before complete power failure occurs. The reset detector monitors power conditions and triggers controlled reset operations in advance, cushioning against the harmful effects of sudden power loss and ensuring continuous reliable operation
Solution Approach 2:
The reset controller serves as an intermediary in the power supply system, mediating between the external power supply and the storage controller. It processes power condition information and generates appropriate reset signals, adding a layer of protection that enhances reliability during power loss without requiring a completely complex power management system
Data Source
AI summary
In a method of resetting a storage device, an internal power supply voltage is generated based on an external power supply voltage. A first reset control signal that is activated when a level of the internal power supply voltage is higher than a reference level. A second reset control signal that is activated after a power-on of the storage device is completed or deactivated after a predetermined delay time from when the external power supply voltage is turned off. A final reset control signal is generated based on the first reset control signal and the second reset control signal. The final reset control signal is activated when at least one of the first and second reset control signals is activated. After the external power supply voltage is turned off, a reset operation is performed when the final reset control signal is activated.