Reconfigurable Storage Interface With Retimer for Low I/O Delay

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Solution Overview

Problem

Current storage systems face challenges in minimizing input and output delays due to the inefficiencies in data transmission and reception processes, particularly when using switches that transmit signals through multiple layers, which can hinder processing speed and performance.

Innovation Solution

The implementation of a storage device set that includes a reconfigurable logic chip with a retimer and an operation circuit, where the retimer adjusts input signals and the operation circuit performs specific operations, allowing for direct data transmission and reception via a physical layer, thereby reducing delays and enhancing processing speed.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a switch is used to transmit signals through multiple layers, then data transmission can be achieved, but input and output delays increase

Engineering Contradiction:

Improvedata transmission capabilityVSAvoidinput and output delay

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the retimer function from the switch and places it directly in the storage device. This separation allows the storage device to perform signal timing adjustment independently, eliminating the need for signals to traverse multiple layers through a switch, thereby reducing input and output delays while maintaining data transmission capability.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The retimer acts as an intermediary component between the host and the storage device controller. By positioning the retimer within the storage device and using it to adjust signal timing before processing, the system optimizes signal transmission without requiring complex multi-layer switch routing, thus reducing delays.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If a dedicated hardware accelerator is used, then processing speed is improved, but adaptability to various applications is reduced

Engineering Contradiction:

Improveprocessing speedVSAvoidapplication-specific adaptability

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

The patent employs a reconfigurable logic chip that can dynamically change its configuration based on different applications. The chip includes operation circuits that can be programmed to perform various operations (e.g., compression, decryption, sorting) depending on the specific task requirements, thus maintaining high processing speed while achieving adaptability to different applications.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The reconfigurable logic chip is designed to perform multiple functions through a single unified architecture. By incorporating programmable operation circuits that can be configured for different operations, the system achieves universal applicability across various applications while maintaining hardware-level processing speed advantages.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS11474714B2Storage device set including storage device and reconfigurable logic chip, and storage system including the storage device set

Publication Date: 2022.10.18 SAMSUNG ELECTRONICS CO LTD

AI summary

A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.