Storage Controller Scaler for High-Speed Data Stream Mapping

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Solution Overview

Problem

Existing storage devices face challenges in reading data streams at high speeds due to the lack of efficient mapping mechanisms for logical addresses of frames within the data stream.

Innovation Solution

A storage device that includes a memory device, a storage controller, and a scaler. The scaler generates a mapping table that maps logical addresses of frames to frame numbers, allowing for batch read requests to be made to the storage controller, which controls the memory device to perform read operations based on these requests.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional sequential read methods are used for data streams, then the storage device can read data, but the reading speed is limited and cannot achieve high-speed data stream processing

Engineering Contradiction:

Improvedata stream reading speedVSAvoidtime for address mapping and read operations

Core Design Contradiction:

SpeedVSLoss of time

Solution Approach 1:

The scaler performs preliminary actions by generating a mapping table that pre-establishes the correspondence between logical addresses and frame numbers before read operations are needed. This allows the storage device to quickly retrieve data by referencing the pre-generated mapping table, avoiding time-consuming address translation during actual read operations and enabling high-speed data stream processing.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If batch read requests are implemented for multiple logical addresses, then reading efficiency improves, but the complexity of address management and mapping increases

Engineering Contradiction:

Improveread operation efficiencyVSAvoidmapping table management complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The mapping table serves as an intermediary data structure that simplifies batch read operations. Instead of directly managing complex relationships between multiple logical addresses and their corresponding physical locations, the system uses the mapping table as a mediator that stores logical address to frame number correspondences. This intermediary layer abstracts the complexity, allowing batch read requests to be efficiently processed by simply looking up pre-stored mappings.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Speed

If logical addresses of multiple frames are read individually, then address mapping can be simple, but the overall data stream processing speed decreases

Engineering Contradiction:

Improvedata stream processing speedVSAvoidbatch request management complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The system merges multiple individual read operations into a single batch read request by utilizing the mapping table. The scaler generates a batch request that combines all necessary logical addresses for a frame group, and the storage controller processes these merged requests in one operation. This merging approach maintains simple address mapping while achieving high processing speed by reducing the number of separate read operations.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250045201A1Storage device

Publication Date: 2025.02.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A method includes generating mapping information in which, for each frame of plural frames stored in a storage component, one or more logical addresses is assigned to the frame and providing a batch read request to the storage component, to read all of the one or more logical addresses assigned to the frame by referring the mapping information.